78Q2120-64CG ETC [List of Unclassifed Manufacturers], 78Q2120-64CG Datasheet - Page 10

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78Q2120-64CG

Manufacturer Part Number
78Q2120-64CG
Description
10/100BASE-TX Ethernet Transceiver
Manufacturer
ETC [List of Unclassifed Manufacturers]
Datasheet
78Q2120
10/100BASE-TX
Ethernet Transceiver
REGISTER DESCRIPTION
The 78Q2120 implements ten 16-bit registers which are accessible via the MDIO and MDC pins. The supported
registers are shown below. Unsupported registers will be read as all zeros. All of the registers respond to the
broadcast address, PHYAD value 00000.
The MII management 16-bit register set implemented in the 78Q2120 is as follows:
Note: MR 3.3:0 contains revision specific data.
LEGEND
TYPE
RC
0/1
R
ADDRESS
8-15
16
17
18
0
1
2
3
4
5
6
7
DESCRIPTION
Readable by management
Cleared on a read operation
Default value upon power-up or reset
SYMBOL
MR8-15
MR16
MR17
MR18
MR0
MR1
MR2
MR3
MR4
MR5
MR6
MR7
NAME
Control
Status
PHY Identifier 1
PHY Identifier 2
Auto-Negotiation Advertisement
Auto-Negotiation Link Partner Ability
Auto-Negotiation Expansion
(Not implemented, read as zero)
(Reserved, read as zero)
Vendor Specific
Interrupt Control/Status Register
Diagnostic Register
TYPE
(0/1)
SC
W
10
DESCRIPTION
Write-able by management
Self clearing, write-able
Default value dependent on pin setting. The value
in brackets indicates typical case.
RESET VALUE (HEX)
(E542)
(01E1)
(3100)
(7809)
(0000)
0300
0000
0000
0000
0000
0540
0000

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