XQ2V1000-4FG456N XILINX [Xilinx, Inc], XQ2V1000-4FG456N Datasheet

XQ2V1000-4FG456N

Manufacturer Part Number

XQ2V1000-4FG456N

Description

QPro Virtex-II 1.5V Platform FPGAs

Manufacturer

XILINX [Xilinx, Inc]

Datasheet

1.XQ2V1000-4FG456N.pdf (134 pages)

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DS122 (v2.0) December 21, 2007

Summary of QPro™ Virtex™-II Features

•

trademarks are the property of their respective owners.

DS122 (v2.0) December 21, 2007

Product Specification

Industry’s first military-grade platform FPGA solution

Certified to MIL-PRF-38535 (Qualified Manufacturer

Listing)

100% factory tested

Guaranteed over the full military temperature range

(–55°C to +125°C) or industrial temperature range

(–40°C to +100°C)

Ceramic and plastic wire-bond and flip-chip grid array

packages

IP-immersion architecture

♦

SelectRAM™ Memory Hierarchy

♦

High-performance interfaces to external memory

♦

Arithmetic functions

♦

Flexible logic resources

Up to 67,584 internal registers/latches with Clock Enable

Up to 67,584 look-up tables (LUTs) or cascadable 16-

bit shift registers

Wide multiplexers and wide-input function support

Horizontal cascade chain and sum-of-products support

Internal 3-state busing

Densities from 1M to 6M system gates

300+ MHz internal clock speed (Advance Data)

622+ Mb/s I/O (Advance Data)

2.5 Mb of dual-port RAM in 18 Kbit block

SelectRAM resources

Up to 1 Mb of distributed SelectRAM resources

DRAM interfaces

SRAM interfaces

CAM interfaces

Dedicated 18-bit x 18-bit multiplier blocks

Fast look-ahead carry logic chains

SDR/DDR SDRAM

Network FCRAM

Reduced Latency DRAM

SDR/DDR SRAM

QDR SRAM

www.xilinx.com

QPro Virtex-II 1.5V Platform FPGAs

•

High-performance clock management circuitry

♦

Active interconnect technology

♦

SelectIO™-Ultra Technology

♦

Supported by Xilinx Foundation Series™ and Alliance

Series™ Development Systems

♦

Up to 12 DCM (Digital Clock Manager) modules

16 global clock multiplexer buffers

Fourth-generation segmented routing structure

Predictable, fast routing delay, independent of fanout

Up to 824 user I/Os

19 single-ended and six differential standards

Programmable sink current (2 mA to 24 mA) per I/O

Digitally Controlled Impedance (DCI) I/O: on-chip

termination resistors for single-ended I/O standards

PCI compliant (32/33 MHz) at 3.3V

Differential signaling

622 Mb/s Low-Voltage Differential Signaling I/O

(LVDS) with current mode drivers

Bus LVDS I/O

Lightning Data Transport (LDT) I/O with current

driver buffers

Low-Voltage Positive Emitter-Coupled Logic

(LVPECL) I/O

Built-in DDR input and output registers

Proprietary high-performance SelectLink

Technology

Integrated VHDL and Verilog design flows

Compilation of 10M system gates designs

Internet Team Design (ITD) tool

Precise clock de-skew

Flexible frequency synthesis

High-resolution phase shifting

High-bandwidth data path

Double Data Rate (DDR) link

Web-based HDL generation methodology

Product Specification

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