WM9705_06 WOLFSON [Wolfson Microelectronics plc], WM9705_06 Datasheet - Page 24

• Manufacturer Part Number: WM9705_06
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM9705
Figure 12 AC-link Audio Output Frame
w
SDATAOUT
BITCLK
SYNC
END OF PREVIOUS
AUDIO FRAME
FRAME
VALID
12.288MHz
TAG PHASE
SLOT(1)
The datastreams currently defined by the AC’97 specification include:
Synchronisation of all AC-link data transactions is signalled by the WM9705 controller. The
WM9705 drives the serial bit clock onto AC-link, which the AC’97 controller then qualifies with a
synchronisation signal to construct audio frames.
SYNC, fixed at 48kHz, is derived by dividing down the serial clock (BITCLK). BITCLK, fixed at
12.288MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and
incoming time slots. AC-link serial data is transitioned on each rising edge of BITCLK. The
receiver of AC-link data, (WM9705 for outgoing data and AC’97 controller for incoming data),
samples each serial bit on the falling edges of BITCLK.
The AC-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a
valid tag for its corresponding time slot within the current audio frame. A 1 in a given bit position
of slot 0 indicates that the corresponding time slot within the current audio frame has been
assigned to a data stream, and contains valid data. If a slot is tagged invalid, it is the
responsibility of the source of the data, (the WM9705 for the input stream, AC’97 controller for the
output stream), to stuff all bit positions with 0s during that slot’s active time.
SYNC remains high for a total duration of 16 BITCLKs at the beginning of each audio frame.
The portion of the audio frame where SYNC is high is defined as the Tag Phase. The remainder
of the audio frame where SYNC is low is defined as the Data Phase. Additionally, for power
savings, all clock, sync, and data signals can be halted. This requires that the WM9705 be
implemented as a static design to allow its Register contents to remain intact when entering a
power savings mode.
PCM playback - 2 output slots
PCM record data - 2 input slots
Control - 2 output slots
Status - 2 input slots
Optional modem line codec output -
1 output slot
Optional modem line codec input –
1 input slot
Optional dedicated microphone input -
1 input slot
SLOT(2)
('1' = TIME SLOT CONTAINS
81.4nS
TIME SLOT 'VALID' BITS
VALID PCM DATA)
SLOT(12)
'0'
'0'
'0'
19
SLOT (1)
0
19
20.8µS (48kHz)
DATA PHASE
SLOT (2)
2-channel composite PCM output stream
2-channel composite PCM input stream
Control Register write port
Control Register read port
Modem line codec DAC input stream
Modem line codec ADC output stream
Dedicated microphone input stream in
support of stereo AEC and/or other voice
applications.
0
19
SLOT (3)
0
PD Rev 4.4 August 2006
19
SLOT (12)
Production Data
0
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