WM9705_06 WOLFSON [Wolfson Microelectronics plc], WM9705_06 Datasheet - Page 27

• Manufacturer Part Number: WM9705_06
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM9705
AC-LINK AUDIO INPUT FRAME (SDATAIN)
Figure 14 AC-link Audio Input Frame
w
SDATAIN
BITCLK
SYNC
END OF PREVIOUS
AUDIO FRAME
CODEC
READY
12.288MHz
TAG PHASE
The audio input frame data streams correspond to the multiplexed bundles of all digital input data
targeting the AC’97 controller. As is the case for audio output frame, each AC-link audio input
frame consists of 12, 20-bit time slots.
Slot 0 is a special reserved time slot containing 16-bits, which are used for AC-link protocol
infrastructure.
Within slot 0 the first bit is a global bit (SDATAIN slot 0, bit 15) which flags whether the WM9705
is in the Codec Ready state or not. If the Codec Ready bit is a 0, this indicates that the WM9705
is not ready for normal operation. This condition is normal following the desertion of power on
reset for example, while the WM9705’s voltage references settle. When the AC-link Codec Ready
indicator bit is a 1, it indicates that the AC-link and the WM9705 control and status registers are in
a fully operational state. The AC’97 controller must further probe the Powerdown Control/Status
Register to determine exactly which subsections, if any, are ready.
Prior to any attempts at putting the WM9705 into operation the AC’97 controller should poll the
first bit in the audio input frame (SDATAIN slot 0, bit 15) for an indication that the WM9705 has
gone Codec Ready.
Once the WM9705 is Codec Ready, then the next 12 bit positions sampled by the AC’97
controller indicate which of the corresponding 12 time slots are assigned to input data streams,
and that they contain valid data. Figure 14 illustrates the time slot based AC-link protocol.
There are several subsections within the WM9705 that can independently go busy/ready. It is the
responsibility of the WM9705 controller to probe more deeply into the WM9705 register file to
determine which of the WM9705 subsections are actually ready.
Figure 15 Start of an Audio Input Frame
SLOT(1)
SDATAIN
SLOT(2)
('1' = TIME SLOT CONTAINS
81.4nS
BITCLK
TIME SLOT 'VALID' BITS
VALID PCM DATA)
SYNC
SLOT(12)
END OF PREVIOUS AUDIO FRAME
'0'
THE WM9705 SAMPLES SYNC ASSERTION HERE
'0'
'0'
AC'97 CONTROLLER SAMPLES FIRST
SDATAIN BIT OF FRAME HERE
19
CODEC
READY
SLOT (1)
0
SLOT (1)
19
20.8 µ S (48kHz)
DATA PHASE
SLOT (2)
SLOT (2)
0
19
SLOT (3)
0
19
SLOT (12)
PD Rev 4.4 August 2006
0
Production Data
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