WM9707_06 WOLFSON [Wolfson Microelectronics plc], WM9707_06 Datasheet - Page 20

• Manufacturer Part Number: WM9707_06
• Description: AC 97 Revision 2.1 Audio CODEC with SPDIF Output
• Manufacturer: WOLFSON [Wolfson Microelectronics plc]

WM9707
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As an example, consider an 8-bit sample stream that is being played out to one of the WM9707’s
DACs. The first 8 bit positions are presented to the DAC (MSB justified) followed by the next 12 bit
positions, which are stuffed with 0s by the AC’97 controller. This ensures that regardless of the
resolution of the implemented DAC (16, 18 or 20-bit), no DC biasing will be introduced by the least
significant bits.
When mono audio sample streams are output from the AC’97 controller, it is necessary that BOTH
left and right sample stream time slots be filled with the same data.
SLOT 1: COMMAND ADDRESS PORT
The command port is used to control features, and monitor status for the WM9707 functions
including, but not limited to, mixer settings, and power management (refer to the Serial Interface
Register Map). The control interface architecture supports up to 64, 16-bit read/write registers,
addressable on even byte boundaries. Only the even Registers (00h, 02h, etc.) are valid. Odd
register read/write will have no effect on the WM9707.
Audio output frame slot 1 communicates control register address, and read/write command
information to the WM9707.
COMMAND ADDRESS PORT BIT ASSIGNMENTS
The first bit (MSB) sampled by the WM9707 indicates whether the current control transaction is a
read or write operation. The following 7 bit positions communicate the targeted control register
address. The trailing 12 bit positions within the slot are reserved and must be stuffed with 0s by the
AC’97 controller.
SLOT 2: COMMAND DATA PORT
The command data port is used to deliver 16-bit control register write data in the event that the
current command port operation is a write cycle. (As indicated by slot 1, bit 19).
If the current command port operation is a read then the entire time slot must be stuffed with 0s by
the AC’97 controller.
SLOT 3: PCM PLAYBACK LEFT CHANNEL
Audio output frame slot 3 is the composite digital audio left playback stream. In a typical Games
Compatible PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the
AC’97 controller or host processor) with music synthesis output samples. If a sample stream of
resolution less than 20-bits is transferred, the AC’97 controller must stuff all trailing non-valid bit
positions within this time slot with 0s.
SLOT 4: PCM PLAYBACK RIGHT CHANNEL
Audio output frame slot 4 is the composite digital audio right playback stream. In a typical Games
Compatible PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the
AC’97 controller or host processor) with music synthesis output samples.
If a sample stream of resolution less than 20-bits is transferred, the AC’97 controller must stuff all
trailing non-valid bit positions within this time slot with 0s.
SLOT 5: OPTIONAL MODEM LINE CODEC
Audio output frame slot 5 contains the MSB justified modem DAC input data. This optional AC’97
feature is not supported in the WM9707, and if data is written to this location it is ignored. This may
be determined by the AC’97 controller interrogating the WM9707 Vendor ID registers.
Bit (19)
Bit (18:12)
Bit (11:0)
Bit (19:4)
Bit (3:0)
Read/write command (1 = read, 0 = write)
Control register index (64 16-bit locations, addressed on even
byte boundaries)
Reserved (stuffed with 0s)
Control register write data (stuffed with 0s if current operation is
a read)
Reserved (stuffed with 0s)
PD Rev 4.1 June 2006
Production Data
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