ISPPAC-POWR1014A LATTICE [Lattice Semiconductor], ISPPAC-POWR1014A Datasheet - Page 20

• Manufacturer Part Number: ISPPAC-POWR1014A
• Description: In-System Programmable Power Supply Supervisor, Reset Generator and Sequencing Controller
• Manufacturer: LATTICE [Lattice Semiconductor]

Lattice Semiconductor
Figure 10. ispPAC-POWR1014/A Macrocell Block Diagram
Clock and Timer Functions
Figure 11 shows a block diagram of the ispPAC-POWR1014/A’s internal clock and timer systems. The master clock
operates at a fixed frequency of 8MHz, from which a fixed 250kHz PLD clock is derived.
Figure 11. Clock and Timer System
The internal oscillator runs at a fixed frequency of 8 MHz. This signal is used as a source for the PLD and timer
clocks. It is also used for clocking the comparator outputs and clocking the digital filters in the voltage monitor cir-
PT4
PT3
PT2
PT1
PT0
Clock
Polarity
Block Init Product Term
Oscillator
Internal
8MHz
SW0
Global Polarity Fuse for
Init Product Term
SW1
MCLK
Product Term Allocation
Global Reset
32
SW2
PLDCLK
20
Power On Reset
Timer 0
Timer 1
Timer 2
Timer 3
ispPAC-POWR1014/A Data Sheet
Macrocell flip-flop provides
D, T, or combinatorial
output with polarity
D/T
PLD Clock
R
CLK
To/From
P
Q
PLD
To PLD Output