ISPPACCLK5316S-01T48C LATTICE [Lattice Semiconductor], ISPPACCLK5316S-01T48C Datasheet - Page 12

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ISPPACCLK5316S-01T48C

Manufacturer Part Number
ISPPACCLK5316S-01T48C
Description
In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet
Lattice Semiconductor
Timing Specifications
Skew Matching
Programmable Skew Control
Control Functions
t
SK
t
t
1. Skew control range is a function of VCO frequency (f
2. Skew step size is a function of VCO frequency (f
3. Only applicable to outputs with non-zero skew settings.
t
t
t
RST_SLEW
1. Will completely reset PLL.
2. Will only reset digital logic.
t
SKRANGE
SKSTEP
SKERR
DIS/OE
PLL_RSTW
RSTW
SKEW
Symbol
In coarse skew mode T
In coarse skew mode T
STEPS
Symbol
Symbol
Output-output Skew
Delay Time, OEX or OEY to Output Disabled/
Enabled
PLL RESET Pulse Width
Logic RESET Pulse Width
Reset Signal Slew Rate
Skew Control Range
Skew Steps per Range
Skew Step Size
Skew Time Error
Parameter
SKRANGE
SKSTEP
Parameter
= 1/(8 x f
= 7/(8 x f
2
Parameter
3
Between any two identically configured and loaded
outputs regardless of bank.
1
VCO
VCO
1
).
2
Fine Skew Mode, f
Fine Skew Mode, f
Coarse Skew Mode, f
Coarse Skew Mode, f
Fine Skew Mode, f
Fine Skew Mode, f
Coarse Skew Mode, f
Coarse Skew Mode, f
Fine skew mode
Coarse skew mode
).
VCO
). In fine skew mode T
VCO
). In fine skew mode T
Conditions
Conditions
VCO
VCO
VCO
VCO
12
VCO
VCO
VCO
VCO
= 160 MHz
= 400 MHz
= 160 MHz
= 400 MHz
= 160 MHz
= 400 MHz
= 160 MHz
= 400 MHz
SKSTEP
Conditions
SKRANGE
= 1/(16 x f
ispClock5300S Family Data Sheet
= 7/(16 x f
Min.
VCO
).
VCO
Min.
Min.
0.1
20
).
1
Typ.
2.73
1.09
5.46
2.19
390
156
780
312
30
50
8
Typ.
Typ.
10
Max.
Max.
Max.
100
20
Units
Units
Units
ns
ps
ps
V/µs
ms
ps
ns
ns

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