A54SX16-2 ACTEL [Actel Corporation], A54SX16-2 Datasheet - Page 3

• Manufacturer Part Number: A54SX16-2
• Description: PCI Arbiter Core
• Manufacturer: ACTEL [Actel Corporation]

Bus P ar ki ng
The arbiter has been designed to implement bus parking;
i.e., it asserts the grant to a default device when none of the
request lines are active (there are no devices are requesting
the bus). This ensures that a requesting device will received
an almost immediate grant. The default case allows the bus
to be parked on the device that last acquired the bus.
However,
BUS_DEVICE, and BUS_GNTN the user can specify the bus
is parked on a device other than the default.
Hidd en Bus A rb it ra ti on
The PCI specification allows bus arbitration to take place
while the currently granted device is performing a data
transfer. This feature greatly reduces arbitration overhead
and improves bus utilization.
Maxi m um L at ency
The device granted the bus must initiate a transaction
(drop FRAMEn signal) within 16 PCI clock cycles. If the
time expires and the device has not initiated a transaction,
the arbiter removes the grant from the device and the bus to
the device with the next highest priority.
Beh avi or al S im ul at ion
The following procedures is used to simulate the VHDL
version of the Arbiter Macro:
Simulating the Pure Rotation Arbiter Scheme
1.
2.
3.
4.
Table 1 • Utilization and Performance Statistics
A54SX16-2
APA750
Invoke the V-System simulator.
Change to the “/vhdl/tbench/mti_arb” directory.
Create a “work” library.
Type the following command at the prompt:
The test bench will be compiled into this directory.
Open the file “arb_wrp.vhd” in the “/vhdl/src” directory
and set the constant ALGORITHM to a one.
vlib work
by
utilizing
Combinatorial
the
Modules
135
84
constants
BUS_PARK,
Sequential
Modules
N/A
Utilization (Estimated)
32
v4.0
5.
6.
Simulating the Fair Rotation Arbiter Scheme
1.
2.
3.
4.
5.
6.
U se r Cod e C us to mi z at ion
The code is currently written to arbit between 5 master
devices. The devices are implemented as states in a finite
state machine (FSR). The end user can modify the
implementation by adding or subtracting states to meet the
number of devices required by the particular application.
E st im a ted P er f or m ance and D evi ce
U t ili z at ion
The expected performance and utilization statistics for the
66 MHz PCI Arbiter using the 54SX16–2 and APA750 devices
are shown in
layout results using automatic place and route.
116 Modules
Resources
Compile the macro and the test bench.
Type the following command at the prompt:
Simulate the test bench.
Type the following command at the prompt:
Invoke the V-System simulator.
Change to the “/vhdl/tbench/mti_arb” directory.
Create a “work” library.
Type the following command at the prompt:
The test bench will be compiled into this directory.
Open the file “arb_wrp.vhd” in the “/vhdl/src” directory
and set the constant ALGORITHM to a zero.
Compile the macro and the test bench.
Type the following command at the prompt:
Simulate the test bench.
Type the following command at the prompt:
135 Tiles
Total
do compall.do
do run_fair.do
vlib work
do compall.do
do run_pure.do
Table
1. These numbers are based on post
Utilization
Percent
0.4%
8%
P C I A r b i t e r C o r e
Max Frequency
Performance
(MHz)
84
71
3