LTM8023EV-PBF LINER [Linear Technology], LTM8023EV-PBF Datasheet - Page 6

• Manufacturer Part Number: LTM8023EV-PBF
• Description: 2A, 36V DC/DC ?Module
• Manufacturer: LINER [Linear Technology]

PIN FUNCTIONS
LTM8023
V
internal regulator and to the internal power switch. This
pin must be locally bypassed with an external, low ESR
capacitor of at least 2.2μF .
V
capacitor and the output load between these pins and
GND pins.
AUX (Pin F5): Low Current Voltage Source for BIAS. In
many designs, the BIAS pin is simply connected to V
The V
adjacent to the BIAS pin to ease printed circuit board rout-
ing. Although this pin is internally connected to V
NOT connect this pin to the load. If this pin is not tied to
BIAS, leave it fl oating.
BIAS (Pin G5): The BIAS pin connects to the internal power
bus. Connect to a power source greater than 2.8V. If the
output is greater than 2.8V, connect this pin there. If the
output voltage is less, connect this to a voltage source
between 2.8V and 16V. Also, make sure that BIAS + V
is less than 56V.
RUN/SS (Pin H5): Tie RUN/SS pin to ground to shut down
the LTM8023. Tie to 2.5V or more for normal operation.
If the shutdown feature is not used, tie this pin to the V
pin. RUN/SS also provides a soft-start function; see the
Applications Information section.
GND (Bank 3): Tie these GND pins to a local ground plane
below the LTM8023 and the circuit components. Return
the feedback divider (R
6
IN
OUT
(Bank 1): The V
(Bank 2): Power Output Pins. Apply the output fi lter
AUX
pin is internally connected to V
IN
pin supplies current to the LTM8023’s
ADJ
) to this net.
OUT
and is placed
OUT
OUT
, do
IN
IN
.
R
frequency of the LTM8023 by connecting a resistor from
this pin to ground. The Applications Information section of
the data sheet includes a table to determine the resistance
value based on the desired switching frequency. Minimize
capacitance at this pin.
SHARE (Pin F7): Tie this to the SHARE pin of another
LTM8023 when paralleling the outputs. Otherwise, do
not connect.
SYNC (Pin G6): This is the external clock synchronization
input. Ground this pin for low ripple Burst Mode operation
at low output loads. Tie to a stable voltage source greater
than 0.7V to disable Burst Mode operation. Do not leave
this pin fl oating . Tie to a clock source for synchronization.
Clock edges should have rise and fall times faster than 1μs.
See synchronizing section in Applications Information.
PGOOD (Pin H6): The PGOOD pin is the open-collector
output of an internal comparator. PG remains low until the
ADJ pin is within 10% of the fi nal regulation voltage. PG
output is valid when V
If this function is not used, leave this pin fl oating.
ADJ (Pin H7): The LTM8023 regulates its ADJ pin to 0.79V.
Connect the adjust resistor from this pin to ground. The
value of R
– 0.79), where R
T
(Pin G7): The R
ADJ
is given by the equation R
ADJ
T
pin is used to program the switching
is in k.
IN
is above 3.6V and RUN/SS is high.
ADJ
= 394.21/(V
8023fb
OUT