ADUM1100ARWZ AD [Analog Devices], ADUM1100ARWZ Datasheet - Page 2

• Manufacturer Part Number: ADUM1100ARWZ
• Manufacturer: AD [Analog Devices]

AN-793
Table I summarizes the ESD test results for the
ADuM140x quad isolator. One might conclude from
Table I that iCouplers can only be used in systems with
ESD ratings of < 4 kV. In reality it is quite common for
iCouplers to be used in systems that pass 15 kV ESD
levels per IEC 61000 - 4 -2.
The difference is in the test methods:
The component-level tests call for direct application
of ESD events to the pins or body of an unpowered
device, while system-level tests call for application ESD
events to various locations in the system accessible to
external ESD occurrences. Furthermore, the specific
waveforms used in component-level and system-level
testing differ.
ESD
Model
Human
Body Model
Field Induced Charge
Device Model
Machine Model
For complete information on Analog Devices ESD testing, refer to the
Analog Devices
To accurately predict the performance of iCouplers in
a system, the designer needs to understand the nature
of the system tests and weigh how they impact the
iCoupler at the component level. Table II lists common
system-level tests used in iCoupler applications. Several
examples of these tests will be discussed later.
Test
Standard
IEC 61000-4-2
IEC 61000-4-4
IEC 61000-4-5
1
iCoupler Model for Analyzing System Test Performance
Figure 2 shows a circuit model of an iCoupler which is
useful to understand the impact of system-level testing.
Inductors L1, L2, L3, and L4 are due largely to package
pins and bond wires, while capacitor C1 is due to the
stray capacitance across the isolation barrier. The induc-
tance values are approximately 0.2 nH. The capacitance
value is approximately 0.3 pF per iCoupler channel.
IEC 61000-4 tests include compliance levels; the test voltages shown
are the ranges for level 1 (lowest) through level 4 (highest) compliance.
Table II. Common System Tests Used
in iCoupler Applications
Table I. ADuM140x ESD Test Results
Reliability
Purpose
ESD
FastTransient/Burst
Surge
Handbook.
First Pass
Voltage (V)
3,500
1,500
200
Test
Voltage (V rms)
2,000 to 15,000
500 to 4,000
500 to 4,000
First Fail
Voltage (V)
4,000
2,000
400
1
–2–
Latch-Up in CMOS Devices
Inherent in a CMOS process are parasitic PNP and
NPN transistors configured as silicon control rectifiers
(SCR). Latch-up is a condition that comes about when
this parasitic SCR is triggered. This causes a low resis-
tance to appear from V
large current to be drawn through the device. This
excessive current lays open the possibility of damage
due to EOS.
Damage caused by latch-up can range from complete
destruction of the device to parametric degradation. More
insidious are latent failures that could affect operation
later in a system’s lifetime. An excellent treatise on
the subject of latch-up in general can be found in the
Analog Dialogue 35 - 05 (2001)
Battle Against Latch- Up in CMOS Switches.” While
this article specifically addresses problems with CMOS
switches, it is generally applicable to all CMOS devices,
including iCouplers.
The use of ceramic bypass capacitors to minimize supply
noise between V
in all iCoupler applications. These should have a value
between 0.01 F and 0.1 F and be placed as close as
possible to the iCoupler device. Even with adequate
bypassing, latch-up problems may still occur in some
applications. Placing a 200  resistor in series with V
also helpful. This limits the supply current to 25 mA in 5 V
applications, which is below the latch-up trigger current.
However, depending on the supply current being drawn,
this series resistance can reduce the supply voltage at
the iCoupler to an unacceptable level. This is most likely
to be a concern when operating at high data rates that
involve high supply currents.
Usually the mechanism that causes latch-up is an over-
voltage condition beyond the part’s absolute maximum
rating (>7.0 V or <–0.5 V for most iCoupler products).
Once an iCoupler is integrated into a system the source
of the overvoltage is not always clear. However, it is
usually manageable once understood.
Figure 2. iCoupler Model Useful in Analyzing
System Designs
GND
V
DD1
V
IN
DD
1
and ground is highly recommended
L1
L3
DD
to ground, and a subsequent
C1
L2
L4
article, “Winning the
V
V
GND
DD2
O
2
REV. 0
DD
is