ISPLSI1032-60LG/883 LATTICE [Lattice Semiconductor], ISPLSI1032-60LG/883 Datasheet - Page 7

• Manufacturer Part Number: ISPLSI1032-60LG/883
• Description: High-Density Programmable Logic
• Manufacturer: LATTICE [Lattice Semiconductor]

1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
PARAMETER
Internal Timing Parameters
Outputs
t
t
t
Clocks
t
t
t
t
t
Global Reset
t
ob
oen
odis
gy0
gy1/2
gcp
ioy2/3
iocp
gr
47
48
49
50
51
52
53
54
55
#
2
Output Buffer Delay
I/O Cell OE to Output Enabled
I/O Cell OE to Output Disabled
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
Clock Delay, Clock GLB to Global GLB Clock Line
Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
Clock Delay, Clock GLB to I/O Cell Global Clock Line
Global Reset to GLB and I/O Registers
DESCRIPTION
1
Specifications ispLSI and pLSI 1032
7
MIN. MAX.
3.6
2.8
0.8
2.8
0.8
–
–
–
–
-90
2.4
4.0
4.0
3.6
4.4
4.0
4.4
4.0
8.2
MIN. MAX.
4.5
3.5
1.0
3.5
1.0
–
–
–
–
-80
3.0
5.0
5.0
4.5
5.5
5.0
5.5
5.0
9.0
1996 ISP Encyclopedia
MIN. MAX.
6.0
4.6
1.3
4.6
1.3
–
–
–
–
-60
12.0
4.0
6.7
6.7
6.0
7.3
6.6
7.3
6.6
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns