ISPLSI2032VE-110LB49 LATTICE [Lattice Semiconductor], ISPLSI2032VE-110LB49 Datasheet - Page 9

• Manufacturer Part Number: ISPLSI2032VE-110LB49
• Manufacturer: LATTICE [Lattice Semiconductor]

Derivations of
Note: Calculations are based on timing specifications for the ispLSI 2032VE-225L.
ispLSI 2032VE Timing Model
Ded. In
Y0,1,2
GOE 0
I/O Pin
Reset
(Input)
t
t
t
su
h
co
2.5ns
7.3ns
2.3ns
I/O Delay
=
=
=
=
=
=
=
=
=
=
=
=
t
#21
#20
su,
Logic + Reg su - Clock (min)
(
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.6 + 0.7 + 2.2) + (6.8) - (0.6 + 0.7 + 0.5)
Clock (max) + Reg h - Logic
(
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.6 + 0.7 + 2.8) + (1.7) - (0.6 + 0.7 + 2.2)
Clock (max) + Reg co + Output
(
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.6 + 0.7 + 2.8) + (0.7) + (1.3 + 1.2)
I/O Cell
t
t
t
io +
io +
io +
t
h and
t
t
t
grp +
grp +
grp +
t
t
t
co from the Product Term Clock
t
20ptxor) + (
ptck(max)) + (
ptck(max)) + (
#45
#43, 44
#42
GRP
GRP
#22
t
gsu) - (
t
t
gh) - (
gco) + (
t
io +
t
io +
Reg 4 PT Bypass
t
orp +
#33, 34,
XOR Delays
Control
PTs
#25, 26, 27
t
Feedback
grp +
t
20 PT
35
grp +
#24
Comb 4 PT Bypass #23
9
t
ob)
RE
OE
CK
t
ptck(min))
t
Specifications ispLSI 2032VE
20ptxor)
GLB
GLB Reg Bypass
D
RST
Table 2-0042/2032VE
GLB Reg
Delay
#28
#29, 30,
31, 32
Q
ORP Bypass
Delay
ORP
ORP
#36
#37
#40, 41
0491/2032VE
#38,
39
I/O Cell
(Output)
I/O Pin