ISPLSI2032VL LATTICE [Lattice Semiconductor], ISPLSI2032VL Datasheet
ISPLSI2032VL
Related parts for ISPLSI2032VL
ISPLSI2032VL Summary of contents
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Features • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 1000 PLD Gates — 32 I/O Pins, Two Dedicated Inputs — 32 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — ...
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Functional Block Diagram Figure 1. ispLSI 2032VL Functional Block Diagram GOE 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 ...
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Absolute Maximum Ratings Supply Voltage V ................................ -0.5 to +4.05V cc Input Voltage Applied ............................. -0.5 to +4.05V Off-State Output Voltage Applied .......... -0.5 to +4.05V Storage Temperature .............................. -65 to +150 C Case Temp. with Power Applied .............. -55 ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.15V from steady-state active level. Output Load Conditions (see Figure 2) TEST ...
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External Timing Parameters 3 TEST PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 t pd2 A 2 Data Propagation Delay Clock Frequency with Internal Feedback max f — 4 Clock Frequency ...
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Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t 22 GRP Delay grp GLB t 4ptbpc 23 4 Product Term Bypass Path Delay (Combinatorial Product ...
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Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset Y0,1,2 GOE Derivations of su, h and co from the Product Term Clock Logic + Reg ...
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Power Consumption Power consumption in the ispLSI 2032VL device de- pends on two primary factors: the speed at which the device is operating and the number of product terms Figure 3. Typical Device Power Consumption vs fmax I CC can ...
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Signal Descriptions Signal Name GOE 0 Global Output Enable Pin Y0 Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. RESET/Y1 This pin performs two functions: (1) Dedicated ...
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Pin Configuration ispLSI 2032VL 44-Pin TQFP Pinout Diagram I/O 28 I/O 29 I VCC BSCAN TDI/IN 0 I/O 0 I pins are not to be connected to any active signals, VCC ...
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Pin Configuration ispLSI 2032VL 48-Pin TQFP Pinout Diagram I/O 28 I/O 29 I/O 30 I/O 31 VCC BSCAN 1 TDI/IN 0 I/O 0 I Pins have dual function capability pins are not ...
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Part Number Description ispLSI 2032VL – XXX Device Family Device Number 2032VL Speed f 180 = 180 MHz max f 135 = 135 MHz max f 110 = 110 MHz max ispLSI 2032VL Ordering Information FAMILY fmax (MHz) tpd (ns) ...