ISPLSI2032VL LATTICE [Lattice Semiconductor], ISPLSI2032VL Datasheet - Page 7

• Manufacturer Part Number: ISPLSI2032VL
• Manufacturer: LATTICE [Lattice Semiconductor]

Derivations of
Note: Calculations are based on timing specifications for the ispLSI 2032VL-180L.
ispLSI 2032VL Timing Model
Ded. In
Y0,1,2
GOE 0
I/O Pin
Reset
(Input)
t
t
t
su
h
co
3.5ns
9.0ns
2.5ns
I/O Delay
=
=
=
=
=
=
=
=
=
=
=
=
t
#21
#20
su,
Logic + Reg su - Clock (min)
(
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.5 + 0.6 + 2.9) + (1.7) - (0.5 + 0.6 + 1.1)
Clock (max) + Reg h - Logic
(
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.5 + 0.6 + 4.1) + (1.3) - (0.5 + 0.6 + 2.9)
Clock (max) + Reg co + Output
(
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.5 + 0.6 + 4.1) + (0.3) + (1.7 + 1.8)
I/O Cell
t
t
t
io +
io +
io +
t
h and
t
t
t
grp +
grp +
grp +
t
t
t
co from the Product Term Clock
t
20ptxor) + (
ptck(max)) + (
ptck(max)) + (
#45
#43, 44
#42
GRP
GRP
#22
t
gsu) - (
t
t
gh) - (
gco) + (
t
io +
t
io +
Reg 4 PT Bypass
t
#33, 34,
orp +
XOR Delays
Control
PTs
#25, 26, 27
Feedback
t
grp +
t
20 PT
35
grp +
#24
Comb 4 PT Bypass #23
7
t
ob)
RE
OE
CK
t
ptck(min))
t
Specifications ispLSI 2032VL
20ptxor)
GLB
GLB Reg Bypass
D
RST
Table 2-0042/2032VL
GLB Reg
Delay
#28
#29, 30,
31, 32
Q
ORP Bypass
Delay
ORP
ORP
#36
#37
#40, 41
0491/2032VL
#38,
39
I/O Cell
(Output)
I/O Pin