F25L16PA-100DG ESMT [Elite Semiconductor Memory Technology Inc.], F25L16PA-100DG Datasheet - Page 17

no-image

F25L16PA-100DG

Manufacturer Part Number
F25L16PA-100DG
Description
3V Only 16 Mbit Serial Flash Memory with Dual
Manufacturer
ESMT [Elite Semiconductor Memory Technology Inc.]
Datasheet
ESMT
Chip Erase
The Chip Erase instruction clears all bits in the device to FFH. A
Chip Erase instruction will be ignored if any of the memory area is
protected. Prior to any Write operation, the Write Enable (WREN)
instruction must be executed. CE must remain active low for
the duration of the Chip-Erase instruction sequence. The Chip
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows reading of
the status register. The status register may be read at any time
even during a Write (Program/Erase) operation.
When a Write operation is in progress, the BUSY bit may be
checked before sending any new commands to assure that the
new commands are properly received by the device.
Elite Semiconductor Memory Technology Inc.
Figure 12: Chip Erase Sequence
Figure 13: Read Status Register (RDSR) Sequence
SCK
SO
CE
SI
MODE0
MODE3
MSB
HIGH IMPENANCE
0 1 2 3 4 5 6 7
60 or C7
Erase instruction is initiated by executing an 8-bit command, 60H
or C7H. CE must be driven high before the instruction is
executed. The user may poll the BUSY bit in the Software Status
Register or wait T
Chip Erase cycle. See Figure 12 for the Chip Erase sequence.
and remain low until the status data is read. Read Status
Register is continuous with ongoing clock cycles until it is
terminated by a low to high transition of the CE . See Figure 13
for the RDSR instruction sequence.
CE must be driven low before the RDSR instruction is entered
CE
for the completion of the internal self-timed
Publication Date: Jul. 2009
Revision: 1.4
F25L16PA
17/33

Related parts for F25L16PA-100DG