A29L004UW-70 AMICC [AMIC Technology], A29L004UW-70 Datasheet - Page 6

• Manufacturer Part Number: A29L004UW-70
• Description: 512K X 8 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
• Manufacturer: AMICC [AMIC Technology]

Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the
selects the device.
array data to the output pins.
the time during read operation. The internal state machine
is set for reading array data upon device power-up, or after
a hardware reset. This ensures that no spurious alteration
of the memory content occurs during the power transition.
No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data
on the device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to
the Read Operations Timings diagram for the timing
waveforms, l
the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive
V
mode to facilitate faster programming. Once the device
enters the Unlock Bypass mode, only two write cycles are
required to program a byte, instead of four.
The “Byte Program Command Sequence” section has
details on programming data to the device using both
standard and Unlock Bypass command sequence. An
erase operation can erase one sector, multiple sectors, or
the entire device. The Sector Address Tables indicate the
address range that each sector occupies. A "sector
address" consists of the address inputs required to uniquely
select a sector. See the "Command Definitions" section for
details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can
then read autoselect codes from the internal register (which
is separate from the memory array) on I/O
read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
I
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
PRELIMINARY
CC2
IL
, and
CE
in the DC Characteristics table represents the active
and
OE
OE
CC1
to V
in the DC Characteristics table represents
pins to V
IH
(October, 2002, Version 0.0)
. The device features an Unlock Bypass
OE
is the output control and gates
IL
.
CE
WE
is the power control and
should remain at V
7
WE
- I/O
0
and
. Standard
CE
IH
all
to
6
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for t
automatic sleep mode is independent of the
provide new data when addresses are changed. While in
sleep mode, output data is latched and always available to
the system. I
the automatic sleep mode current specification.
Output Disable Mode
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section
for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the
input.
The device enters the CMOS standby mode when the
& RESET pins (
packages) are both held at VCC
more restricted voltage range than V
(N/A on 32-pin PLCC & (s)TSOP packages) are held at V
but not within VCC
mode, but the standby current will be greater. The device
requires the standard access time (t
read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
I
standby current specification.
Automatic Sleep Mode
When the
disabled. The output pins are placed in the high impedance
state.
OE
CC3
and I
control signals. Standard address access timings
7
- I/O
CC4
OE
in the DC Characteristics tables represent the
CC4
0
. Standard read cycle timings and I
input is at V
in the DC Characteristics table represents
CE
0.3V, the device will be in the standby
only on 32-pin PLCC & (s)TSOP
AMIC Technology, Corp.
IH
, output from the device is
A29L004 Series
0.3V. (Note that this is a
CE
IH
) before it is ready to
.) If
ACC
CE
CE
+30ns. The
and RESET
,
WE
CC
read
OE
CE
and
IH
,