M66257 Mitsubishi, M66257 Datasheet - Page 2

• Manufacturer Part Number: M66257
• Description: 5120 x 8-BIT x 2 LINE MEMORY (FIFO)
• Manufacturer: Mitsubishi

2
FUNCTION
When write enable input WE is “L”, the contents of data inputs
D
chronization with rise edge of write clock input WCK. At this
time, the write address counter of 1-line delay data only
memory is also incremented simultaneously.
The write functions given below are also performed in syn-
chronization with rise edge of WCK.
When WE is “H”, a write operation to 1-line delay data only
memory is inhibited and the write address counter of 1-line
delay data only memory is stopped.
When write reset input WRES is “L”, the write address counter
of 1-line delay data only memory is initialized.
When read enable input RE is “L”, the contents of 1-line delay
data only memory are output to data outputs Q
those of 2-line delay data only memory to data outputs Q
Q
At this time, the read address counters of 1-line and 2-line
delay data only memories is also incremented simulta-
neously.
0
17
to D
in synchronization with the rise of read clock input RCK.
7
are written into 1-line delay data only memory in syn-
00
to Q
07
10
and
to
Moreover, data of Q
only memory in synchronization with rise edge of RCK. At
this time, the write address of 2-line delay data only memory
is incremented.
The read functions given below are also performed in syn-
chronization with rise edge of RCK.
When RE is “H”, a read operation from both of 1-line delay
data only memory and 2-line delay data only memory is inhib-
ited and the read address counter of each memory is
stopped. The outputs of Q
high impedance state.
Moreover, a write operation to 2-line delay data only memory
is inhibited and the write address counter of 2-line delay data
only memory is stopped.
When read reset input RRES is “L”, the read address counter
of 1-line delay data only memory, and the write address
counter and read address counter of 2-line delay data only
memory are initialized.
5120
00
to Q
MITSUBISHI DIGITAL ASSP
07
00
8-BIT
are written into 2-line delay data
to Q
07
2 LINE MEMORY (FIFO)
and Q
M66257FP
10
to Q
17
are in the