AT89C1051 ATMEL Corporation, AT89C1051 Datasheet
AT89C1051
Available stocks
Related parts for AT89C1051
AT89C1051 Summary of contents
Page 1
... Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51™ instruction set. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C1051 is a pow- erful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications ...
Page 2
... Block Diagram V CC RAM ADDR. REGISTER GND B REGISTER TIMING INSTRUCTION RST AND REGISTER CONTROL ANALOG COMPARATOR + OSC AT89C1051 4-4 RAM ACC TMP2 TMP1 ALU INTERRUPT, AND TIMER BLOCKS PSW PORT 1 LATCH - PORT 1 DRIVERS P1.0 - P1.7 FLASH PROGRAM STACK ADDRESS POINTER REGISTER BUFFER PC INCREMENTER PROGRAM ...
Page 3
... As inputs, Port 3 pins that are externally being pulled low will source current (I ) because of the pullups. IL Port 3 also serves the functions of various special features of the AT89C1051 as listed below: Port Pin Alternate Functions P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3 ...
Page 4
... AT89C1051. This should be the responsibility of the software programmer. For example, LJMP 3FEH would be a valid instruction for the AT89C1051 (with 1K of memory), whereas LJMP 410H would not. TL0 TH0 ...
Page 5
... MOVX-related instructions, Data Memory: The AT89C1051 contains 64 bytes of internal data mem- ory. Thus, in the AT89C1051 the stack depth is limited to 64 bytes, the amount of available RAM. External DATA memory access is not supported in this device, nor is exter- nal PROGRAM memory execution. Therefore, no MOVX [ ...
Page 6
... P3.1 is pulled Low during programming to indicate RDY/BSY. AT89C1051 4-8 Data Polling: The AT89C1051 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the com- plement of the written data on P1.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin ...
Page 7
... The write operation cycle is self- timed and once initiated, will automatically time itself to completion. Figure 4. Verifying the Flash Memory PGM P1 DATA SEE FLASH PROGRAMMING MODES TABLE RST AT89C1051 V CC PGM DATA P3.3 P3.4 P3.5 P3.7 XTAL1 RST GND ...
Page 8
... Data Float After ENABLE EHQZ t PROG High to BUSY Low GHBL t Byte Write Cycle Time WC t RDY/BSY to Increment Clock Delay BHIH t Increment Clock High IHIL Note: Only used in 12-volt programming mode. Flash Programming and Verification Waveforms AT89C1051 4-10 Min 11.5 1.0 1.0 1 1.0 200 Max Units 12.5 ...
Page 9
Absolute Maximum Ratings Operating Temperature ........................-55°C to +125°C Storage Temperature ...........................-65°C to +150°C Voltage on Any Pin with Respect to Ground........................... -1.0V to +7.0V Maximum Operating Voltage...................................6.6V DC Output Current ............................................25 Characteristics T = -40°C to 85°C, V ...
Page 10
... CLCX t Rise Time CLCH t Fall Time CHCL AC Testing Input/Output Waveforms Note Inputs during testing are driven at V logic 1 and 0.45V for a logic 0. Timing measurements are made at V min. for a logic 1 and V IH logic 0. AT89C1051 4- 2.7V to 6.0V CC Min Max 0 12 83.3 41 (1) Float Waveforms - 0 ...
Page 11
... TYPICAL ICC - ACTIVE (85° Vcc=5. FREQUENCY (MHz) AT89C1051 TYPICAL ICC - IDLE (85° Vcc=5. FREQUENCY (MHz) AT89C1051 TYPICAL ICC vs. VOLTAGE- POWER DOWN (85° 3.0V 4.0V Vcc VOLTAGE (power down) Vcc=6.0V Vcc=3. Vcc=6.0V Vcc=3. 5.0V 6.0V 4-13 ...
Page 12
... Supply Ordering Code 12 2.7V to 6.0V AT89C1051-12PC AT89C1051-12SC AT89C1051-12PI AT89C1051-12SI AT89C1051-12PA AT89C1051-12SA 24 4.0V to 6.0V AT89C1051-24PC AT89C1051-24SC AT89C1051-24PI AT89C1051-24SI 20P3 20 Lead, 0.300” Wide, Plastic Dual In-line Package (PDIP) 20S 20 Lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC) AT89C1051 4-14 Package 20P3 20S 20P3 ...