ISL6532 Intersil Corporation, ISL6532 Datasheet - Page 11

• Manufacturer Part Number: ISL6532
• Description: ACPI Regulator/Controller for Dual Channel DDR Memory Systems
• Manufacturer: Intersil Corporation

the modulator is simply the input voltage (V
peak-to-peak oscillator voltage ∆V
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6532) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R
R
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high
gain peak due to the high Q factor of the output filter and is
not shown in Figure 6. Using the above guidelines should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at FP2 with the
capabilities of the error amplifier. The Closed Loop Gain is
constructed on the graph of Figure 6 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
Z
overall loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
F LC
F
F
1. Pick Gain (R
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
2. Place 1
FB
3
Z1
Z2
, C
=
and Z
=
=
FB
1
------------------------------------------ -
2π x
, C
----------------------------------- -
2π x R
------------------------------------------------------ -
2π x R
. The goal of the compensation network is to provide
2
IN
ST
, and C
ND
ST
ND
0dB
(
1
L O x C O
to provide a stable, high bandwidth (BW)
1
2
Zero Below Filter’s Double Pole (~75% F
1
Pole at the ESR Zero.
Zero at Filter’s Double Pole.
Pole at Half the Switching Frequency.
x C
) and adequate phase margin. Phase margin
1
+
2
R
/R
2
3
3
) in Figure 5. Use these guidelines for
1
) x C
) for desired converter bandwidth.
3
11
F ESR
F
F
P1
P2
=
=
OSC
=
-------------------------------------------------------- -
2π x R
----------------------------------- -
2π x R
------------------------------------------- -
2π x ESR x C O
.
1
2
3
IN
1
x
x C
) divided by the
1



C
--------------------- -
C
3
1
1
x C
+
0dB
C
2
2
LC
1



, R
IN
and
).
2
,
ISL6532
Output Voltage Selection
The output voltage of the VDDQ PWM converter can be
programmed to any level between VIN and the internal
reference, 0.8V. An external resistor divider is used to scale
the output voltage relative to the reference voltage and feed
it back to the inverting input of the error amplifier, see
Figure 6.
However, since the value of R1 affects the values of the rest
of the compensation components, it is advisable to keep its
value less than 5kW. Depending on the value chosen for R1,
R4 can be calculated based on the following equation:
If the output voltage desired is 0.8V, simply route V
to the FB pin through R1, but do not populate R4.
The output voltage for the internal V
internal to the ISL6532 to track the V
There is no need for external programming resistors.
Component Selection Guidelines
Output Capacitor Selection - PWM Buck Converter
An output capacitor is required to filter the inductor current
and supply the load transient current. The filtering
requirements are a function of the switching frequency and
the ripple current. The load transient requirements are a
function of the slew rate (di/dt) and the magnitude of the
transient load current. These requirements are generally met
with a mix of capacitors and careful layout.
DDR memory systems are capable of producing transient
load rates above 1A/ns. High frequency capacitors initially
supply the transient and slow the current load rate seen by the
bulk capacitors. The bulk filter capacitor values are generally
determined by the ESR (Effective Series Resistance) and
voltage rating requirements rather than actual capacitance
requirements.
R4
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
100
-20
-40
-60
80
60
40
20
0
=
---------------------------------- -
V
10
(R
R1
DDQ
20LOG
MODULATOR
2
/R
×
1
–
0.8V
GAIN
)
100
0.8V
1K
F
Z1
F
FREQUENCY (Hz)
LC
F
Z2
10K
F
F
P1
ESR
(V
100K
IN
20LOG
TT
F
/∆V
DDQ
P2
OSC
linear regulator is set
OPEN LOOP
ERROR AMP GAIN
voltage by 50%.
1M
)
COMPENSATION
CLOSED LOOP
10M
GAIN
GAIN
DDQ
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