V23814-K1306-M136 Infineon Technologies, V23814-K1306-M136 Datasheet - Page 10

• Manufacturer Part Number: V23814-K1306-M136
• Description: PAROLI Tx AC/ 1.25 Gbit/s
• Manufacturer: Infineon Technologies

Receiver V23815-K1306-M136
The PAROLI receiver module converts parallel optical input signals into parallel electrical
output signals. The optical signals received are converted into voltage signals by PIN
diodes, transimpedance amplifiers, and gain amplifiers. There are two different modules
available for LVDS and Infineon’s adjustable CML output. This description only refers to
a module with LVDS output. A module description for CML output can be provided
separately.
The data rate is up to 1250 Mbit/s for each channel. The receiver module’s min. data rate
of 500 Mbit/s is specified for the CID
with a lower disparity.
Additional Signal Detect outputs (SD1 active high / SD12 active low) show whether an
optical AC input signal is present at data input 1 and/or 12. The signal detect circuit can
be disabled with a logic low at ENSD. The disabled signal detect circuit will permanently
generate an active level at Signal Detect outputs, even if there is insufficient signal input.
This could be used for test purposes.
A logic low at LVDS Output Enable (OEN) sets all data outputs to logic low. SD outputs
will not be effected.
All non data signals have LVCMOS levels.
Transmission delay of the PAROLI system is at a maximum 1 ns for the transmitter, 1 ns
for the receiver and approximately 5 ns per meter for the fiber optic cable.
Figure 3
1)
Data Sheet
Consecutive Identical Digit (CID) immunity test pattern for STM-N signals,
ITU-T recommendation G.957 sec. II.
Optical
Input
Data
12
Receiver Block Diagram
Pin
Diode
Array
12
Amplifier
1)
worst case pattern (disparity 72) or any pattern
10
Gain
Amplifier
Signal
Detect
Circuit
ENSD
Output Enable (OEN)
12
LVDS
Output
Stage
V23814-K1306-M136
V23815-K1306-M136
12
Data out
Electrical
Output
SD1
-SD12
Description
2001-12-01