ADG511 Analog Devices, ADG511 Datasheet
ADG511
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ADG511 Summary of contents
Page 1
... ADG512. The ADG513 contains two switches whose digital control logic is similar to that of the ADG511 while the logic is inverted in the remaining two switches. PRODUCT HIGHLIGHTS 1. +5 Volt Single Supply Operation ...
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... ADG511/ADG512/ADG513–SPECIFICATIONS Dual Supply ( 10 Parameter +25 C ANALOG SWITCH Analog Signal Range LEAKAGE CURRENTS Source OFF Leakage I (OFF) 0.025 S 0.1 Drain OFF Leakage I (OFF) 0.025 D 0.1 Channel ON Leakage (ON) 0. 0.2 DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL ...
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... ADG511/ADG512/ADG513 Units Test Conditions/Comments V DD typ –10 mA max typ V = 4.5 4 max Test Circuit 2 nA typ V = 4.5 4 ...
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... ADG511/ADG512/ADG513–SPECIFICATIONS Single Supply (V = +3 Parameter ANALOG SWITCH Analog Signal Range R ON LEAKAGE CURRENTS Source OFF Leakage I (OFF) S Drain OFF Leakage I (OFF) D Channel ON Leakage (ON DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current INL ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG511/ADG512/ADG513 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... ADG511 ADG512 ADG513 TOP VIEW GND 5 12 (Not to Scale IN4 CONNECT Truth Table (ADG511/ADG512) ADG511 ADG512 Truth Table (ADG513) Switch Logic OFF 1 ON TERMINOLOGY IN2 D2 GND S2 S ...
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... – DRAIN OR SOURCE VOLTAGE – Figure 3. On Resistance as a Function of V Single Supply REV. B Typical Performance Graphs–ADG511/ADG512/ADG513 10mA 1mA 100 100nA 10nA Figure 4. Supply Current vs. Input Switching Frequency (V ) Dual D ...
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... TRENCH ISOLATION V = –5V SS The MOS devices that make up the ADG511A/ADG512A/ ADG513A are isolated from each other by an oxide layer (trench) (see Figure 10). When the NMOS and PMOS devices are not electrically isolated from each other, there exists the possibility of “latch-up” caused by parasitic junctions between CMOS transistors ...
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... 35pF 300 V OUT2 5. Break-Before-Make Time Delay OUT C L 10nF V OUT V GND Charge Injection –9– ADG511/ADG512/ADG513 Leakage 3V 50% 50% 3V 50% 50% 90% 90 OFF 3V V 50% 50 90% 90% 0V 90% ...
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... ADG511/ADG512/ADG513 Test Circuits (continued 0 GND SS 0 Off Isolation V OUT V IN1 OUT Channel-to-Channel Crosstalk –10– 0 IN2 GND SS CHANNEL TO CHANNEL 0.1 F CROSSTALK = 20 LOG ...
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... PIN 1 0.0098 (0.25) 0.0532 (1.35) 0.0040 (0.10) 0.0500 0.0192 (0.49) SEATING 0.0099 (0.25) (1.27) 0.0138 (0.35) PLANE BSC 0.0075 (0.19) –11– ADG511/ADG512/ADG513 0.325 (8.26) 0.195 (4.95) 0.300 (7.62) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 15° 0.008 (0.20) 0° 0.0196 (0.50 0.0099 (0.25 0.0500 (1.27) 0.0160 (0.41) ...