HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 190
HD6417021
Manufacturer Part Number
HD6417021
Description
SuperH RISC engine
Manufacturer
Hitachi Semiconductor
Datasheet
1.HD6417021.pdf
(507 pages)
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9.2.3
DMA transfer count registers 0-3 (TCR0–TCR3) are 16-bit read/write registers that specify the
DMA transfer count (bytes or words). The number of transfers is 1 when the setting is H'0001,
65535 when the setting is H'FFFF and 65536 (the maximum) when H'0000 is set. During a DMA
transfer, these registers indicate the remaining transfer count. The initial value after resets or in
standby mode is undefined.
9.2.4
DMA channel control registers 0–3 (CHCR0–CHCR3) are 16-bit read/write registers that control
the DMA transfer mode. They also indicate DMA transfer status. They are initialized to H'0000 by
a reset or standby mode.
Notes: 1. Write only 0 to clear the flag.
Initial value:
Initial value:
Initial value:
Initial value:
2. Writing is effective only for CHCR0 and CHCR1.
Bit name:
Bit name:
Bit name:
Bit name:
DMA Transfer Count Registers 0–3 (TCR0–TCR3)
DMA Channel Control Registers 0–3 (CHCR0–CHCR3)
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
R/(W)
DM1
R/W
R/W
R/W
AM
15
—
—
15
7
0
7
0
*2
R/(W)
DM0
R/W
R/W
R/W
AL
14
—
—
14
6
0
6
0
*2
R/(W)
SM1
R/W
R/W
R/W
DS
13
—
—
13
5
0
5
0
*2
SM0
R/W
R/W
R/W
R/W
TM
12
—
—
12
4
0
4
0
R/W
R/W
RS3
R/W
R/W
TS
11
—
—
11
3
0
3
0
R/W
R/W
RS2
R/W
R/W
10
—
—
10
IE
2
0
2
0
R/(W)*
R/W
R/W
RS1
R/W
TE
—
—
9
1
9
0
1
0
HITACHI 175
R/W
R/W
RS0
R/W
R/W
DE
—
—
8
0
8
0
0
0
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