HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 409

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

The receive margin in the asynchronous mode can therefore be expressed as in equation 1.
Equation 1:
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation 2.
Equation 2:
This is a theoretical value. A reasonable margin to allow in system designs is 20–30%.
Constraints on DMAC Use:
HITACHI 396
Synchronization
data (RxD)
base clock
sampling
sampling
M =
M:
N:
D:
L:
F:
D
M
Receive
Internal
timing
timing
Figure 13.21 Receive Data Sampling Timing in Asynchronous Mode
Data
0.5 –
Receive margin (%)
Ratio of clock frequency to bit rate (N = 16)
Clock duty cycle (D = 0–1.0)
Frame length (L = 9–12)
Absolute deviation of clock frequency
= 0.5, F = 0
= (0.5 – 1/(2
= 46.875%
0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5
2 N
8 clocks
Start bit
1
– ( L – 0.5) F –
16 clocks
16))
(2)
100%
–7.5 clocks
D
–
N
0.5
+7.5 clocks
(1 + F )
D0
100%
D1