SAF-C161S-L25M Infineon Technologies AG, SAF-C161S-L25M Datasheet - Page 54
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SAF-C161S-L25M
Manufacturer Part Number
SAF-C161S-L25M
Description
16-Bit Single-Chip Microcontroller
Manufacturer
Infineon Technologies AG
Datasheet
1.SAF-C161S-L25M.pdf
(75 pages)
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Quantity
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Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx
registers and represent the special characteristics of the programmed memory cycle.
Table 15
Table 15
Description
ALE Extension
Memory Cycle Time Waitstates
Memory Tristate Time
Note: Please respect the maximum operating frequency of the respective derivative.
5.4
Table 16
ALE cycle time = 6 TCL + 2
Parameter
ALE high time
Address setup to ALE
Address hold after ALE
ALE falling edge to RD,
WR (with RW-delay)
ALE falling edge to RD,
WR (no RW-delay)
Address float after RD,
WR (with RW-delay)
Address float after RD,
WR (no RW-delay)
Data Sheet
describes, how these variables are to be computed.
AC Characteristics
Memory Cycle Variables
Multiplexed Bus (Standard Supply Voltage Range)
(Operating Conditions apply)
Symbol
t
t
t
t
t
t
t
5
6
7
8
9
10
11
t
A
+
t
C
CC 10 +
CC 4 +
CC 10 +
CC 10 +
CC -10 +
CC –
CC –
+
Symbol
t
t
t
A
C
F
t
F
Min.
Max. CPU Clock
(120 ns at 25 MHz CPU clock without waitstates)
t
= 25 MHz
A
50
t
t
t
A
A
A
t
A
Values
TCL
2TCL
2TCL
Max.
–
–
–
–
–
6
26
<ALECTL>
(15 - <MCTC>)
(1 - <MTTC>)
1 / 2TCL = 1 to 25 MHz
Min.
TCL - 10
+
TCL - 16
+
TCL - 10
+
TCL - 10
+
-10 +
–
–
Variable CPU Clock
t
t
t
t
A
A
A
A
Timing Characteristics
t
A
Max.
–
–
–
–
–
6
TCL + 6
V1.0, 2003-11
C161S
Unit
ns
ns
ns
ns
ns
ns
ns