HD643303x Hitachi, HD643303x Datasheet - Page 282

• Manufacturer Part Number: HD643303x
• Description: Hitachi Microcomputer
• Manufacturer: Hitachi

Table 8-11 (d) ITU Operating Modes (Channel 3)
Operating Mode
Synchronous preset
PWM mode
Output compare A
Output compare B
Input capture A
Input capture B
Counter By compare
clearing
Complementary
PWM mode
Reset-synchronized
PWM mode
Buffering
(BRA)
Buffering
(BRB)
Legend:
Notes: 1. Master enable bit settings are valid only during waveform output.
2. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
3. Do not set both channels 3 and 4 for synchronous operation when complementary PWM mode is selected.
4. The counter cannot be cleared by input capture A when reset-synchronized PWM mode is selected.
5. In complementary PWM mode, select the same clock source for channels 3 and 4.
6. Use the input capture A function in channel 1.
o
match/input
capture A
By compare
match/input
capture B
Syn-
chronous
clear
Setting available (valid). — Setting does not affect this mode.
TSNC
Synchro-
nization
SYNC3 = 1 —
o
o
o
o
o
o
o
SYNC3 = 1 —
o
o
o
o
*3
MDF
—
—
—
—
—
—
—
—
—
—
—
TMDR
FDIR PWM
—
—
—
—
—
—
—
—
—
—
—
—
—
o
PWM3 = 1 CMD1 = 0
PWM3 = 0 CMD1 = 0
o
PWM3 = 0 CMD1 = 0
PWM3 = 0 CMD1 = 0
o
o
o
—
—
o
o
Comple-
mentary
PWM
o
CMD1 = 0
Illegal setting:
CMD1 = 1
CMD0 = 0
CMD1 = 0
Illegal setting:
CMD1 = 1
CMD0 = 0
CMD1 = 1
CMD0 = 0
CMD1 = 1
CMD0 = 1
o
o
*3
Reset-
Synchro-
nized PWM Buffering
o
CMD1 = 0
CMD1 = 0
CMD1 = 0
CMD1 = 0
CMD1 = 0
o
CMD1 = 0
o
CMD1 = 1
CMD0 = 0
CMD1 = 1
CMD0 = 1
o
o
*4
TFCR
267
Register Settings
o
o
o
o
o
o
o
o
o
o
o
BFA3 = 1
Other bits
unrestricted
BFB3 = 1
Other bits
unrestricted
XTGD Select Enable
—
—
—
—
—
—
—
—
—
o
o
—
—
*6
*6
TOCR
Output
Level
—
—
—
—
—
—
—
—
—
o
o
—
—
TOER
Master
o
o
o
o
EA3 ignored IOA2 = 1
Other bits
unrestricted unrestricted
EA3 ignored
Other bits
unrestricted
o
o
o
o
o
o
o
*1
*1
*1
*1
*1
*1
IOA
o
—
IOA2 = 0
Other bits
unrestricted
o
Other bits
o
o
o
o
—
—
o
o
TIOR3
IOB
o
o
o
IOB2 = 0
Other bits
unrestricted
o
IOA2 = 1
Other bits
unrestricted
o
o
o
—
—
o
o
*2
Clear
Select
o
o
o
o
o
o
CCLR1 = 0
CCLR0 = 1
CCLR1 = 1
CCLR0 = 0
CCLR1 = 1
CCLR0 = 1
CCLR1 = 0
CCLR0 = 0
CCLR1 = 0
CCLR0 = 1
o
o
TCR3
Clock
Select
o
o
o
o
o
o
o
o
o
o
o
o
o
*5