Z89139 Zilog., Z89139 Datasheet
Z89139
Related parts for Z89139
Z89139 Summary of contents
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... IBM is a registered trademark of IBM Corporation. programs can be directed by events in each other’s do- main. The Z89139 is the ROMless version of the Z89138. How- ever, the on-chip DSP is not ROMless. Notes: All Signals with a preceding front slash, "/", are ac- tive Low. For example, B//W (WORD is active Low); /B/W (BYTE is active Low, only) ...
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... Z89138/Z89139 Voice Processing Controllers GENERAL DESCRIPTION (Continued) Power connections follow conventional descriptions be- low: Connection Circuit Power V CC Ground GND Z8 Core Processor The on-chip Z8 is Zilog’s 8-bit microcontroller core with an Expanded Register File to allow access to register- mapped peripheral and I/O circuits. The Z8 offers a flexible ...
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... RAM 0 Internal Address Bus 6K Words Program DSP Core ROM Internal Data Bus INT 1 INT 2 Extended Bus of the DSP Timer 2 Timer Z89138/Z89139 Voice Processing Controllers P31 P32 Input P33 Port 3 P34 Output P35 P36 P37 P40 ...
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... Z89138/Z89139 Voice Processing Controllers PIN DESCRIPTION (Continued P06 P05 P04 P03 85 P02 P01 P00 GND P17 90 P16 P15 P14 P13 P12 95 P11 P10 GND AGND VREF- 100 ANIN 1 Figure 2. Z89138 100-Pin QFP Pin Configuration 100-Pin QFP 5 10 ...
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... Input/Output Port 5, Bit 0-1 No Connection Input Crystal Input (32.768 kHz) Output Crystal Output (32.768 kHz) No Connection No Connection Input/Output Port 0, Bit 7-0 Input/Output Port 1, Bit 7-0 Analog GND Input Analog Voltage Ref- Input Analog Input Z89138/Z89139 Voice Processing Controllers Function 5 1 ...
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... Z89138/Z89139 Voice Processing Controllers PIN DESCRIPTION (Continued P07 P06 P05 80 P04 P03 P02 P01 P00 85 GND P17 P16 P15 P14 P13 90 P12 P11 P10 GND AGND 95 VREF- ANIN VREF+ ANVDD 100 1 Figure 3. Z89138 100-Pin VQFP Pin Configuration 6 70 ...
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... Output 54-74 76, 77 78-85 Input/Output 87-94 Input/Output 96 97 Input 98 Input Z89138/Z89139 Voice Processing Controllers Symbol Digital Ground Digital VCC = +5V Analog Voltage Ref+ Analog VDD PWM Output Control Input DSP User Output 1, 0 Address Strobe Data Strobe Read/Write No Connection Port 5 Bit 7-4 Crystal Output (20 ...
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... P02 P01 P00 GND P17 90 P16 P15 P14 P13 P12 95 P11 P10 GND AGND VREF- 100 ANIN 1 Figure 4. Z89139 100-Pin QFP Pin Configuration 100-Pin QFP VCC P51 ...
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... Zilog Table 3. Z89139 100-Pin QFP Pin Identification I/O Port Symbol Pin Number GND 3, 53, 88 16, 47 VREF+ 1 ANV 2 DD PWM 4 DSP1 /AS 8 /DS 9 R// P57-P54 12-15 XTAL2 17 XTAL1 18 P53-P52 19, 20 P37-P34 21-24 P33-P31 25-27 /RESET 28 P20-P27 29-36 P40-P47 37-44 P50-P51 45 48-52 OSC1 54 OSC2 ...
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... P00 85 GND P17 P16 P15 P14 P13 90 P12 P11 P10 GND AGND 95 VREF- ANIN VREF+ ANVDD 100 1 Figure 5. Z89139 100-Pin VQFP Pin Configuration 100-Pin VQFP VCC ...
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... Zilog Table 4. Z89139 100-Pin VQFP Pin Identification I/O Port Symbol Pin Number GND 1, 51, 86 14, 45 VREF+ ANV 100 DD PWM DSP1 /AS /DS R//W NC P57-P54 10-13 XTAL2 XTAL1 P53-P52 17, 18 P37-P34 19-22 P33-P31 23-25 /RESET P20-P27 27-34 P40-P47 35-42 P50-P51 43 46-50 OSC1 OSC2 NC 54-74 NC 76, 77 ...
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... Z89138/Z89139 Voice Processing Controllers ABSOLUTE MAXIMUM RATINGS Sym Description Min V Supply –0.3 CC Voltage (*) T Storage Temp –65 STG T Oper. A Ambient Temp. Notes: *Voltage on all pins with respect to GND. †See Ordering Information. STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted ...
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... CC CC 5.0V GND –0.3 0 5.0V V –0.4 CC 5.0V 0.4 5.0V 1.2 5. 5.0V GND –0.3 5.0V 5.0V –10 5.0V –10 5. Z89138/Z89139 Voice Processing Controllers Typical @ 25 C Units Conditions See Note 2 2.5 V Driven by External Clock Generator 1.5 V Driven by External Clock Generator 2.5 V 1 –2 ...
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... Z89138/Z89139 Voice Processing Controllers DC ELECTRICAL CHARACTERISTICS Z89138 A/D Converter V Sym Parameter I Input Leakage 5.5V IL Analog Input I Input Leakage 5.5V IH Analog Input I Input Current 5.5V VREFH I Input Current 5.5V VREFL I Input Current 5.5V VEFL I Input Current 5.5V VREFL + Min Max Units DD 1.00 2.00 1. –2. ...
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... Input Current IL P31, P32, P33 DS97TAD0201 + Min Max DD 5.5V 6.00 5.5V 6.00 5.5V 1.00 5.5V 1.00 5.5V 1.00 5.5V 30 5.5V 30 5.5V 1.20 5.5V 0.60 5.5V 4.00 5.5V 4.00 5.5V 1.00 5.5V 1. Z89138/Z89139 Voice Processing Controllers Units Conditions ...
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... Z89138/Z89139 Voice Processing Controllers AC CHARACTERISTICS External I/O or Memory Read and Write Timing Diagram R//W 12 Port 0, /DM 19 Port 1 1 /AS 4 /DS (Read) Port1 /DS (Write) Figure 7. External I/O or Memory Read/Write Timing OUT ...
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... Note [4] Min 5.0V 25 5.0V 35 5.0V 5.0V 35 5.0V 0 5.0V 125 5.0V 75 5.0V 5.0V 0 5.0V 40 5.0V 35 5.0V 25 5.0V 35 5.0V 40 5.0V 25 5.0V 5.0V 48 5.0V 50 5.0V 20 for a logic Z89138/Z89139 Voice Processing Controllers Max Units Notes ns 2,3 ns 2,3 150 ns 1,2 1,2,3 ns 1,2 1,2,3 ns 2,3 ns 2,3 ns 2,3 ns 2,3 ns 2,3 ns 2,3 ns 2,3 180 ns 1,2,3 ns 2,3 ns 1,2,3 ns ...
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... Z89138/Z89139 Voice Processing Controllers AC ELECTRICAL CHARACTERISTICS Additional Timing Diagram Clock 7 7 TIN 4 IRQN 8 Clock Setup Stop Mode Recovery Source Figure 8. Additional Timing Zilog DS97TAD0201 ...
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... Z89138/Z89139 Voice Processing Controllers Units Notes [4] ms ...
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... Z89138/Z89139 Voice Processing Controllers AC ELECTRICAL CHARACTERISTICS Handshake Timing Diagrams Data In 1 /DAV (Input) RDY (Output) Data Out /DAV (Output) RDY (Input) 20 Data In Valid 2 3 Delayed DAV 4 Figure 9. Input Handshake Timing Data Out Valid Figure 10. Output Handshake Timing ...
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... RDY Rise to DAV Fall Delay Note: 5.0V 0.5V DS97TAD0201 + Note Min 5.0V 0 5.0V 0 5.0V 40 5.0V 5.0V 5.0V 0 5.0V TpC 5.0V 0 5.0V 5. Z89138/Z89139 Voice Processing Controllers Data Max Units Direction OUT ns OUT 70 ns OUT ns OUT ...
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... Z89138/Z89139 Voice Processing Controllers PIN FUNCTIONS /RESET (input, active Low). This pin initializes the MCU. Reset is accomplished either through Power-On Reset (POR), Watch-Dog Timer (WDT) reset, Stop-Mode Recov- ery, or external reset. During POR and WDT Reset, the in- ternally generated reset signal is driving the reset pin Low for the POR time ...
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... Port 1 and the control sig- nals /AS, /DS, and R//W (Figure 11). 4 Port 0 (I/O or A15 - A8) 4 MCU Handshake Controls /DAV0 and RDY0 (P32 and P35) 2.3V Hysteresis R = 500 K Figure 11. Port 0 Configuration Z89138/Z89139 Voice Processing Controllers Pad Auto Latch 23 1 ...
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... Z89138/Z89139 Voice Processing Controllers PIN FUNCTIONS (Continued) Port 1 (P17-P10). Port 8-bit, bidirectional, CMOS compatible port (Figure 12). It has multiplexed Address (A7-A0) and Data (D7-D0) ports. These eight I/O lines are programmed as inputs or outputs, or can be configured un- der software control as an Address/Data port for interfac- ing external memory ...
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... Port 2 (I/O) Z89138/139 MCU Handshake Controls /DAV2 and RDY2 (P31 and P36) 1.5 2.3V Hysteresis R = 500 K Figure 13. Port 2 Configuration Z89138/Z89139 Voice Processing Controllers Pad Auto Latch 25 1 ...
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... Z89138/Z89139 Voice Processing Controllers PIN FUNCTIONS (Continued) Port 3 (P37-P31). Port 7-bit, CMOS compatible port with three fixed inputs (P33-P31) and four fixed outputs (P37-P34 configured under software control for in- put/output, counter/timers, interrupt, and port handshakes. Pins P31, P32, and P33 are standard CMOS inputs; out- puts are push-pull ...
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... Recovery Source DS97TAD0201 Z89138/139 MCU R247 = P3M D1 DIG Figure 14. Port 3 Configuration Z89138/Z89139 Voice Processing Controllers Port 3 (I/O or Control Analog 0 = Digital IRQ2 P31 Data IN Latch IRQ0, P32 Data Latch IRQ1, P33 Data Latch 1 27 ...
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... Z89138/Z89139 Voice Processing Controllers PIN FUNCTIONS (Continued) Port 4 (P47-P40). Port 8-bit, bidirectional, CMOS compatible I/O port (Figure 15). These eight I/O lines are configured under software control independently as inputs or outputs. Port 4 is always available for I/O operation. The input buffers are Schmitt-triggered. Bits programmed as outputs can be globally programmed as either push-pull or open-drain ...
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... Whether this level cannot be determined. A valid CMOS level, rather than a floating node, reduces exces- sive supply current flow in the input buffer. Port 5 Z89138/139 (I/O) MCU 2.3V Hysteresis R = 500 K Figure 16. Port 5 Configuration Z89138/Z89139 Voice Processing Controllers Pad Auto Latch 29 1 ...
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... Z89138/Z89139 Voice Processing Controllers Z8 FUNCTIONAL DESCRIPTION The Z8 core of the Z89138/139 incorporates special func- tions to enhance the Z8’s application in a variety of voice- processing applications. Reset. The device is reset in one of the following condi- tions: Power-On Reset Watch-Dog Timer Stop-Mode Recovery Source External Reset Program Memory ...
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... Group 13 (D) Group 4 (4) Specified Working Group 3 (3) Group 2 (2) Group 1 (1) Group 0 (0) I/O Ports Figure 20. Register Pointer Z89138/Z89139 Voice Processing Controllers Expanded Register File Bank Working Register Group R255 R253 R240 R239 R223 ...
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... Z89138/Z89139 Voice Processing Controllers Z8 FUNCTIONAL DESCRIPTION (Continued) REGISTER POINTER Working Register Expanded Register Group Pointer Bank Pointer Z8 Reg. File FFH FOH 7FH 0FH 0 00H Notes Unknown † = For ROMless mode, RESET Condition 10110110 Will not be Reset with a Stop-Mode Recovery * Figure 21 ...
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... External (P32), Programmable Rise or Fall Edge Triggered 2, 3 External (P33), Fall Edge Triggered 4, 5 External (P31), Programmable Rise or Fall Edge Triggered 6, 7 Internal (DSP activated), Fall Edge Triggered 8, 9 Internal 10, 11 Internal Z89138/Z89139 Voice Processing Controllers IRQ Register (D6, D7) 6 Comments 33 1 ...
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... Z89138/Z89139 Voice Processing Controllers Z8 FUNCTIONAL DESCRIPTION (Continued) When more than one interrupt is pending, priorities are re- solved by a programmable priority encoder controlled by the Interrupt Priority Register. An interrupt machine cycle is activated when an interrupt request is granted. This dis- ables all subsequent interrupts, pushes the Program ...
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... Register 6-Bit 4 Down Counter 6-Bit Down Counter PRE1 Initial Value Register Write Write Figure 24. Counter/Timer Block Diagram Z89138/Z89139 Voice Processing Controllers Internal Data Bus Read T0 T0 Initial Value Current Value Register Register 8-bit Down Counter IRQ4 T ...
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... Z89138/Z89139 Voice Processing Controllers Z8 FUNCTIONAL DESCRIPTION (Continued) Port Configuration Register (PCON). The PCON regis- ter configures the comparator output on Port 3. The PCON register (Figure 25) is located in the Expanded Register File at Bank F, location 00H. Comparator Output Port 3 (D0). Bit 0 controls the com- parator use in Port 3 ...
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... P2 NOR 0-3 111 P2 NOR 0-7 R Always "1" W Stop Delay 0 OFF 1 ON* R Always "1" Low Stop Recovery Level* 1 High Stop Recovery Level R Always "1" effect R 0 POR* 1 Stop-Mode Recovery Z89138/Z89139 Voice Processing Controllers 37 1 ...
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... Z89138/Z89139 Voice Processing Controllers Z8 FUNCTIONAL DESCRIPTION (Continued) SCLK/TCLK divide-by-16 Select (D0 the SMR controls a divide-by-16 prescaler of SCLK/TCLK. The pur- pose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT Mode (where TCLK sources counter/timers and interrupt logic). ...
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... If the DSP was in HALT Mode, this bit is automatically pre- set to 1. Writing a 0 has no effect. Z8 SCLK (D7-D6). These bits define the SCLK frequency of the Z8. The oscillator can be divided After a reset, both bits default to 00 Z89138/Z89139 Voice Processing Controllers Label (OSC/8) (OSC/4) (OSC/2) Return “ ...
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... Z89138/Z89139 Voice Processing Controllers Z8 FUNCTIONAL DESCRIPTION (Continued) Watch-Dog Timer Mode Register (WDTMR). The WDT is a retriggerable one-shot timer that resets the reaches its terminal count. The WDT is initially enabled by executing the WDT instruction and refreshed on subse- quent executions of the WDT instruction. The WDT circuit ...
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... RC oscillator. Clear 18 Clock RESET CLK Generator WDT TAP SELECT 100 POR M CK WDT/POR Counter Chain U CLR X Figure 30. Resets and WDT Z89138/Z89139 Voice Processing Controllers RESET Internal RESET 1 41 ...
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... Z89138/Z89139 Voice Processing Controllers DSP REGISTERS DESCRIPTION General. The DSP is a high-performance second genera- tion CMOS Digital Signal Processor with a modified Har- vard-type architecture with separate program and data ports. The design has been optimized for processing pow- er and saving silicon space. ...
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... Outgoing Registers Incoming Registers DSP Interrupt Control Register D/A and A/D Data Registers D9 D2 Analog Control Register Figure 31. Z8-DSP Interface Attrib R/W R/W R/W R/W R/W R/W R/W R Z89138/Z89139 Voice Processing Controllers EXT0 EXT1 EXT2 EXT3 EXT0 EXT1 EXT2 EXT3 EXT4 EXT5 EXT6 Value Label %NN (B)00/DSP_ext0_hi %NN ...
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... Z89138/Z89139 Voice Processing Controllers DSP REGISTERS DESCRIPTION (Continued) Table 13. Z8 Incoming Registers (Write-Only from DSP) Field Position Incoming [8] (B)08 76543210 Incoming [9] (B)09 76543210 Incoming [a] (B)0A 76543210 Incoming [b] (B)0B 76543210 Incoming [c] (B)0C 76543210 Incoming [d] (B)0D 76543210 Incoming [e] (B)0E 76543210 Incoming [f] (B)0F 76543210 Field Position DSP_ext0 fedcba9876543210 Mail Box DSP_ext1 fedcba9876543210 ...
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... Interrupt Request Logic Figure 32. DSP Interrupts INT0 INT1 INT2 INT2 INT0 Figure 33. DSP Interrupt Priority Structure Figure 34. Interprocessor Interrupts Structure Z89138/Z89139 Voice Processing Controllers INT2 INT2 INT1 INT1 Interrupt Mask Logic INT0 INT0 CLEAR_INT0 CLEAR_INT1 CLEAR_INT2 ENABLE_INT ...
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... Z89138/Z89139 Voice Processing Controllers DSP REGISTERS DESCRIPTION (Continued) Table 15. EXT4 DSP Interrupt Control Register (ICR) Definition Field Position DSP_IRQ2 f--------------- f--------------- DSP_IRQ1 -e-------------- -e-------------- DSP_IRQ0 --d------------- --d------------- DSP_MaskINT2 ---c------------ DSP_MaskINT1 ----b----------- DSP_MaskINT0 -----a---------- Z8_IRQ3 ------9--------- ------9--------- DSPintEnable -------8-------- DSP_IPR2 --------7------- DSP_IPR1 ---------6------ DSP_IPR0 ----------5----- Clear_IRQ2 -----------4---- -----------4---- Clear_IRQ1 ------------3--- ------------3--- Clear_IRQ0 -------------2-- -------------2-- Reserved --------------10 46 ...
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... INT2 INT1 INT1 INT2 INT2 INT0 INT1 INT0 INT0 INT2 INT0 INT1 Reserved Reserved Reserved Reserved Z89138/Z89139 Voice Processing Controllers RP,#%0F r12,#%01 RP D/A_INT is switched to INT0 INT0 INT1 INT2 INT1 INT2 Reserved Reserved 1 47 ...
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... Z89138/Z89139 Voice Processing Controllers DSP Analog Data Registers The D/A conversion is DSP driven by sending 10-bit data to the EXT5 of the DSP. The six remaining bits of EXT5 are not used (Figure 35 A/D supplies 8-bit data to the DSP through the register EXT5 of the DSP ...
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... User-defined DSP outputs R/W 1 A/D Enabled 0 A/D Disabled W No effect R 1 Done 0 Not Done R/W 1 Start 0 Wait Timer R Return “0” effect R/W 1 29.49 MHz* 0 20.48 MHz† R Z89138/Z89139 Voice Processing Controllers 20.48 29.49 MHz MHz* 16 kHz 8.04 kHz 10 kHz 9.6 kHz 16 kHz 16 kHz 8 kHz 9.6 kHz 49 1 ...
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... Z89138/Z89139 Voice Processing Controllers DSP IRQ0. This bit defines the source of the DSP IRQ0 in- terrupt. D/A_Sampling Rate. This field defines the sampling rate of the D/A output. It changes the period to Timer3 interrupt and the maximum possible accuracy of the D/A Sampling Rate (Table 18). Table 18. D/A Data Accuracy ...
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... The remaining one slot in each group has nine time slots set to logic 1. For 10 kHz PWM, the effective output frequency is 10K 320 kHz. Figure 40 illustrates the waveform by using a 6-bit PWM data (3-bit High_Val and 3-bit Low_Val). 250 Z89138/Z89139 Voice Processing Controllers 10 kHz 16 kHz 51 1 ...
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... Z89138/Z89139 Voice Processing Controllers Figure 39. PWM Waveform of the Active Region 52 (for a 6-bit PWM data Zilog DS97TAD0201 ...
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... The errors of the con- verter will increase and the conversion time can also take slightly longer due to smaller input signals Z89138/Z89139 Voice Processing Controllers – 4-Bit + ...
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... Z89138/Z89139 Voice Processing Controllers SCLK P32 Input Sample A/D Result DSP INT DSP Write Notes: 1. SCLK = 10 MHz (XTAL = 20.48 MHz) Figure 42 shows the input circuit of the ADC. When con- version starts, the analog input voltage from the input is connected to the MSB and LSB flash converter inputs as shown in the Input Impedance CKT diagram ...
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... Figure 48. Outgoing Register to DSP EXT2 ( DSP EXT1, Bits D15-D8 Figure 49. Outgoing Register to DSP EXT3 DSP EXT1, Bits D7- Z89138/Z89139 Voice Processing Controllers DSP EXT2, Bits D15-D8 (High Byte) (B) 04H [Read/Write] DSP EXT2, Bits D7-D0 (Low Byte) ...
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... Z89138/Z89139 Voice Processing Controllers ( Figure 50. Outgoing Register to DSP EXT3 (Low Byte) (B) 07H [Read/Write] ( Figure 51. Incoming Register from DSP EXT0 (High Byte) (B) 08H [Read-Only] ( Figure 52. Incoming Register from DSP EXT0 ...
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... Data Figure 64. Port 4 and 5 Configuration Register P40-P47 I/O Definition 0 Defines Bit as Output 1 Defines Bit as Input Returns "FF" Upon Read Z89138/Z89139 Voice Processing Controllers Data Figure 62. Port 5 Data Register (F) 04H [Read/Write] P50-P57 I/O Definition 0 Defines Bit as Output 1 Defines Bit as Input* Returns " ...
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... Z89138/Z89139 Voice Processing Controllers SMR (FH) 0BH Default Setting After Reset † Reset After Stop-Mode Recovery Figure 65. Stop-Mode Recovery Register (SMR SCLK/TCLK not divided by 16† 1 SCLK/TCLK divided Always "1" Reserved W 000 POR only* 001 No effect ...
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... WDT During STOP 0 OFF 1 ON* XTAL1/INT RC Select for WDT 0 On-Board RC 1 XTAL W No effect R Always "1" Figure 66. Watch-Dog Timer Mode Register (F) 0FH [Read/Write Z89138/Z89139 Voice Processing Controllers Value Label 00 OSC/8 01 OSC/4 1x OSC/2 Return “0” ...
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... Z89138/Z89139 Voice Processing Controllers Z8 CONTROL REGISTERS R240 Figure 67. Reserved (F0H) R241 TMR Figure 68. Timer Mode Register (F1H: Read/Write) R242 Figure 69. Counter/Timer 1 Register (F2H: Read/Write) 60 R243 PRE1 ...
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... P34 = /DM R249 IPR P34 = / P34 = RDY1//DAV1 * * P36 = Output (TOUT) P36 = RDY2//DAV2 P37 = Output Z89138/Z89139 Voice Processing Controllers P00 - P03 Mode 00 Output * 01 Input 1X A11 - A8 Stack Selection 0 External * 1 Internal P10 - P17 Mode ...
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... Z89138/Z89139 Voice Processing Controllers Z8 CONTROL REGISTERS (Continued) R250 IRQ Figure 77. Interrupt Request Register (FAH: Read/Write) R251 IMR Figure 78. Interrupt Mask Register (FBH: Read/Write) R252 FLAGS Figure 79. Flag Register (FCH: Read/Write) ...
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... Zilog PACKAGE INFORMATION DS97TAD0201 Figure 83. 100-Pin QFP Package Diagram Figure 84. 100-Pin VQFP Package Diagram Z89138/Z89139 Voice Processing Controllers 63 1 ...
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... A = Very Small Quad Flatpack (VQFP) Temperature Example: Z 89138 Z89138 (29 MHz) 100-Pin QFP 100-Pin VQFP Z8913829FSC Z8913829ASC Z89139 (29 MHz) 100-Pin QFP 100-Pin VQFP Z8913929FSC Z8913929ASC Speeds 20 = 20.48 MHz 29 = 29.49 MHz Environmental C = Plastic Standard is a Z89138, 20.48 MHz, QFP +55 C, Plastic Standard Flow ...
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... Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com Z89138/Z89139 Voice Processing Controllers 65 1 ...
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... Z89138/Z89139 Voice Processing Controllers Zilog DS97TAD0201 ...