Z89175 Zilog., Z89175 Datasheet - Page 36

• Manufacturer Part Number: Z89175
• Description: Voice Processing Controllers
• Manufacturer: Zilog.

Z8
Z89175/Z89176
Voice Processing Controllers
When more than one interrupt is pending, priorities are re-
solved by a programmable priority encoder controlled by
the Interrupt Priority Register. An interrupt machine cycle
is activated when an interrupt request is granted. This dis-
ables all subsequent interrupts, pushes the Program
Counter and Status Flags to the stack, and then branches
to the program memory vector location reserved for that in-
terrupt.
All Z8 interrupts are vectored through locations in the pro-
gram memory. This memory location and the next byte
contain the 16-bit address of the interrupt service routine
for that particular interrupt request. To accommodate
polled interrupt systems, interrupt inputs are masked and
the Interrupt Request Register can be polled to determine
which of the interrupt requests needs service.
An interrupt resulting from AN1 is mapped into IRQ2, and
an interrupt from AN2 is mapped into IRQ0. Interrupts
IRQ2 and IRQ0 can be rising, falling or both edge trig-
gered, and are programmable by the user. The software
can poll to identify the state of the pin.
36
Name
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
®
Table 6. Interrupt Types, Sources, and Vectors
FUNCTIONAL DESCRIPTION (Continued)
/DAV0, P32,
/DAV2, P31,
/DAV1, P33
TIN, AN2
Source
IRQ3
AN2
T0
TI
Location
Vector
10, 11
0, 1
2, 3
4, 5
6, 7
8, 9
External (P32),
Programmable Rise
or Fall Edge
Triggered
External (P33), Fall
Edge Triggered
External (P31),
Programmable Rise
or Fall Edge
Triggered
Internal (DSP
activated), Fall Edge
Triggered
Internal
Internal
Comments
P R E L I M I N A R Y
Programming bits for the Interrupt Edge Select are located
in the IRQ Register (R250), bits D7 and D6 . The configu-
ration is shown in Table 7.
Notes:
F = Falling Edge
R = Rising Edge
Clock. The Z89175/176 on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to a crystal, LC,
ceramic resonator, or any suitable external clock source
(XTAL1 = Input, XTAL2 = Output). The crystal should be
AT cut, 20.48 MHz maximum, with a series resistance
(RS) less than or equal to 100 Ohms. The system clock
(SCLK) is one half the crystal frequency.
The crystal is connected across XTAL1 and XTAL2 using
capacitors from each pin to Ground (Figure 23).
D7
0
0
1
1
IRQ
Table 7. IRQ Register
D6
0
1
0
1
P31
R/F
R
F
F
Interrupt Edge
DS97TAD0100
P32
R/F
R
F
F
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