24LC21 MicrochipTechnology, 24LC21 Datasheet - Page 5

no-image

24LC21

Manufacturer Part Number
24LC21
Description
1K2.5VDualModeI2CSerialEEPROM
Manufacturer
MicrochipTechnology
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
24LC21
Quantity:
5 510
Part Number:
24LC21-I/P
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
24LC21-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
24LC21-I/SN
Manufacturer:
MICROCHIP
Quantity:
12 000
Part Number:
24LC21-I/SN
Manufacturer:
MIC
Quantity:
1 000
Part Number:
24LC21-I/SN
Manufacturer:
MIC
Quantity:
20 000
Part Number:
24LC21/P
Manufacturer:
Microchip Technology
Quantity:
1 792
Part Number:
24LC21/P
Manufacturer:
NSMDA
Quantity:
5 510
Part Number:
24LC21/P
Manufacturer:
MICR
Quantity:
20 000
Company:
Part Number:
24LC21/SN
Quantity:
1 370
Part Number:
24LC211
Manufacturer:
ST
0
Part Number:
24LC211
Manufacturer:
ST
Quantity:
20 000
3.0
The 24LC21 can be switched into the Bi-Directional
Mode (see Figure 3-1) by applying a valid high to low
transition on the Bi-Directional Mode Clock (SCL).
When the device has been switched into the Bi-Direc-
tional Mode, the VCLK input is disregarded, with the
exception that a logic high level is required to enable
write capability. This mode supports a two wire bi-direc-
tional data transmission protocol. In this protocol, a
device that sends data on the bus is defined to be the
transmitter, and a device that receives data from the
bus is defined to be the receiver. The bus must be con-
trolled by a master device that generates the Bi-Direc-
tional Mode Clock (SCL), controls access to the bus
and generates the START and STOP conditions, while
the 24LC21 acts as the slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated.
FIGURE 3-1:
FIGURE 3-2:
1996 Microchip Technology Inc.
SCL
SDA
VCLK
SDA
BI-DIRECTIONAL MODE
SCL
T
SU
:
STA
MODE TRANSITION
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
START
Transmit Only Mode
T
HD
:
STA
T
VHZ
Bi-Directional Mode
3.1
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
• During data transfer, the data line must remain
Accordingly, the following bus conditions have been
defined (see Figure 3-2).
3.1.1
Both data and clock lines remain HIGH.
3.1.2
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.1.3
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
V
not busy.
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
HYS
Bi-Directional Mode Bus
Characteristics
BUS NOT BUSY (A)
START DATA TRANSFER (B)
STOP DATA TRANSFER (C)
T
SU
:
STO
STOP
24LC21
DS21095F-page 5

Related parts for 24LC21