24LC21 MicrochipTechnology, 24LC21 Datasheet - Page 7

• Manufacturer Part Number: 24LC21
• Description: 1K2.5VDualModeI2CSerialEEPROM
• Manufacturer: MicrochipTechnology

3.1.6
After generating a START condition, the bus master
transmits the slave address consisting of a 7-bit device
code (1010) for the 24LC21, followed by three don’t
care bits.
The eighth bit of slave address determines if the master
device wants to read or write to the 24LC21 (see
Figure 3-5).
The 24LC21 monitors the bus for its corresponding
slave address all the time. It generates an acknowledge
bit if the slave address was true and it is not in a pro-
gramming mode.
FIGURE 3-5:
FIGURE 4-1:
Operation
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
VCLK
1996 Microchip Technology Inc.
Read
Write
1
START
SLAVE ADDRESS
0
Control Code
SLAVE ADDRESS
1
CONTROL BYTE
ALLOCATION
BYTE WRITE
1010
1010
S
S
T
A
R
T
0
CONTROL
X
Chip Select
READ/WRITE
BYTE
XXX
XXX
X
R/W
X
R/W
A
A
C
K
1
0
ADDRESS
WORD
4.0
4.1
Following the start signal from the master, the slave
address (4 bits), the don’t care bits (3 bits) and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24LC21. After receiving
another acknowledge signal from the 24LC21 the mas-
ter device will transmit the data word to be written into
the addressed memory location. The 24LC21 acknowl-
edges again and the master generates a stop condi-
tion. This initiates the internal write cycle, and during
this time the 24LC21 will not generate acknowledge
signals (see Figure 4-1).
It is required that VCLK be held at a logic high level in
order to program the device. This applies to byte write
and page write operation. Note that VCLK can go low
while the device is in its self-timed program operation
and not affect programming.
4.2
The write control byte, word address and the first data
byte are transmitted to the 24LC21 in the same way as
in a byte write. But instead of generating a stop condi-
tion the master transmits up to eight data bytes to the
24LC21 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains con-
stant. If the master should transmit more than eight
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (see Figure 4-2).
It is required that VCLK be held at a logic high level in
order to program the device. This applies to byte write
and page write operation. Note that VCLK can go low
while the device is in its self-timed program operation
and not affect programming.
WRITE OPERATION
Byte Write
Page Write
A
C
K
DATA
24LC21
DS21095F-page 7
A
C
K
P
S
T
O
P