24LC32A-MT MicrochipTechnology, 24LC32A-MT Datasheet - Page 9

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24LC32A-MT

Manufacturer Part Number
24LC32A-MT
Description
32KI2CSerialEEPROMinISOMicromodule
Manufacturer
MicrochipTechnology
Datasheet
8.3
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24LC32A transmits the
first data byte, the master issues an acknowledge as
opposed to the stop condition used in a random read.
This acknowledge directs the 24LC32A to transmit the
FIGURE 8-2:
FIGURE 8-3:
next sequentially addressed 8 bit word (see Figure 8-
3). Following the final byte transmitted to the master,
the master will NOT generate an acknowledge but will
generate a stop condition.
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
1997 Microchip Technology Inc.
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
Sequential Read
RANDOM READ
SEQUENTIAL READ
S
T
A
R
T
S
1
CONTROL
0 1
CONTROL
BYTE
BYTE
0
0 0 0 0
A
C
K
A
C
K
DATA n
0 0 0 0
HIGH BYTE
ADDRESS
A
C
K
A
C
K
DATA n +1
LOW BYTE
ADDRESS
To provide sequential reads the 24LC32A contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation. The internal address pointer will
automatically roll over from address 0FFF to address
000 if the master acknowledges the byte received from
the array address 0FFF.
24LC32A MODULE
A
C
K
DATA n +2
S
T
A
R
T
A
C
K
S
1
0 1
CONTROL
BYTE
0
0 0 0 1
A
C
K
A
C
K
DATA n + X
BYTE
DATA
DS21225A-page 9
N
O
A
C
K
N
O
A
C
K
S
T
O
P
S
T
O
P

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