AT25P1024C1-10CC ATMEL Corporation, AT25P1024C1-10CC Datasheet
AT25P1024C1-10CC
Related parts for AT25P1024C1-10CC
AT25P1024C1-10CC Summary of contents
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... Description The AT25P1024 provides 1,048,576 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT25P1024 is available in space saving 20-pin JEDEC SOIC and 8-pin leadless array (LAP) packages ...
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The AT25P1024 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self- timed, and no separate ...
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Pin Capacitance Applicable over recommended operating range from T Test Conditions C Output Capacitance (SO) OUT C Input Capacitance (CS, SCK, SI HOLD) IN Note: 1. This parameter is characterized and is not 100% tested. DC Characteristics ...
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AC Characteristics Applicable over recommended operating range from TTL Gate and 100 pF (unless otherwise noted). L Symbol Parameter f SCK Clock Frequency SCK t Input Rise Time RI t Input Fall Time FI t SCK ...
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AC Characteristics (Continued) Applicable over recommended operating range from TTL Gate and 100 pF (unless otherwise noted). L Symbol Parameter t Hold to Output Low Hold to Output High Output ...
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Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25P1024 always operates as a slave. TRANSMITTER/RE CEIV ER: The AT25P 1024 has separate pins designated for ...
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... The AT25P1024 is divided into four array segments. Top quarter (1/4), top half (1/2), or all of the memory seg- ments can be protected. Any of the data within any selected segment will therefore be READ only. The block write protection levels and corresponding status register control bits are shown in Table 4 ...
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... AT25P1024, two separate instructions must be executed. First, the device must be write enabled via the Write Enable (WREN) Instruction. Then a Write (WRITE) Instruc- tion may be executed. Also, the address of the memory location( programmed must be outside the pro- tected address field location selected by the Block Write ...
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Timing Diagrams (for SPI Mode 0 (0, 0)) Synchronous Data Timing CSS V IH SCK HI WREN Timing WRDI Timing t t ...
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RDSR Timing CS 0 SCK INSTRUCTION SI HIGH IMPEDANCE SO WRSR Timing READ Timing SCK SI INSTRUCTION HIGH IMPEDANCE SO AT25P1024 MSB ...
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WRITE Timing SCK SI INSTRUCTION HIGH IMPEDANCE SO HOLD Timing CS SCK HOLD 3-BYTE ADDRESS ...
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... MAX (kHz) Ordering Code 2100 AT25P1024C1-10CC AT25P1024W1-10SC 2100 AT25P1024C1-10CI AT25P1024W1-10SI 1400 AT25P1024C1-10CC-2.7 AT25P1024W1-10SC-2.7 1000 AT25P1024C1-10CI-2.7 AT25P1024W1-10SI-2.7 500 AT25P1024C1-10CC-1.8 AT25P1024W1-10SC-1.8 500 AT25P1024C1-10CI-1.8 AT25P1024W1-10SI-1.8 Package Type Options Package Operation Range 8C1 Commercial 20S ( 8C1 Industrial 20S (- 8C1 Commercial ...
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Packaging Information 8C1, 8-Lead, 0.300" Wide, Leadless Array Package (LAP) Dimensions in Inches and (Millimeters) TOP VIEW 5.15 (0.203) 4.85 (0.191) 8.15 (0.321) 7.85 (0.309) BOTTOM VIEW 1.27 (0.050) TYP 0.64 (0.025) ...