AT49F010-12JC ATMEL Corporation, AT49F010-12JC Datasheet - Page 2

• Manufacturer Part Number: AT49F010-12JC
• Description: 1-Megabit 128K x 8 5-volt Only CMOS Flash Memory
• Manufacturer: ATMEL Corporation

gram cycle has been detected, a new access for a read or
program can begin. The typical number of program and
erase cycles is in excess of 10,000 cycles.
Block Diagram
Device Operation
READ: The AT49F010/HF010 is accessed like an
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the ad-
dress pins is asserted on the outputs. The outputs are put
in the high impedance state whenever CE or OE is high.
This dual-line control gives designers flexibility in prevent-
ing bus contention.
ERASURE: Before a byte can be reprogrammed, the
128K bytes memory array (or 120K bytes if the boot block
featured is used) must be erased. The erased state of the
memory bits is a logical “1". The entire device can be
erased at one time by using a 6-byte software code. The
chip erase code consists of 6-byte load commands to spe-
cific address locations with a specific data pattern (please
refer to the Chip Erase Cycle Waveforms).
After the chip erase has been initiated, the device will in-
ternally time the erase operation so that no external clocks
are required. The maximum time needed to erase the
whole chip is t
been enabled, the data in the boot sector will not be
erased.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0") on a
byte-by-byte basis. Please note that a data ”0" cannot be
programmed back to a “1"; only erase operations can con-
vert ”0"s to “1"s. Programming is accomplished via the in-
ternal device command register and is a 4 bus cycle op-
eration (please refer to the Command Definitions table).
The device will automatically generate the required inter-
nal program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified t
2
AT49F010/HF010
EC
. If the boot block lockout feature has
BP
cy-
The optional 8K bytes boot block section includes a repro-
gramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
cle time. The DATA polling feature may also be used to
indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The de-
vice has one designated block that has a programming
lockout feature. This feature prevents programming of
data in the designated block once the feature has been
enabled. The size of the block is 8K bytes. This block, re-
ferred to as the boot block, can contain secure code that
is used to bring up the system. Enabling the lockout fea-
ture will allow the boot code to stay in the device while data
in the rest of the device is updated. This feature does not
have to be activated; the boot block’s usage as a write
protected region is optional to the user. The address range
of the boot block is 00000H to 01FFFH.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular
programming method. To activate the lockout feature, a
series of six program commands to specific addresses
with specific data must be performed. Please refer to the
Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the
boot block section is locked out. When the device is in the
software product identification mode (see Software Prod-
uct Identification Entry and Exit sections) a read from ad-
dress location 00002H will show if programming the boot
block is locked out. If the data on I/O0 is low, the boot
block can be programmed; if the data on I/O0 is high, the
program lockout feature has been activated and the block
cannot be programmed. The software product identifica-
tion code should be used to return to standard operation.