M24256-A STMicroelectronics, M24256-A Datasheet
M24256-A
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M24256-A Summary of contents
Page 1
... These I C-compatible electrically erasable pro- grammable memory (EEPROM) devices are orga- nized as 32Kx8 bits, and operate down to 2.5 V (for the M24256-AW), and down to 1.8 V (for the M24256-AR). The M24256-A is available in Plastic Dual-in-Line, Plastic Small Outline and Thin Shrink Small Out- line packages ...
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... SDA SCL 1 Parameter PSDIP8: 10 sec SO8: 40 sec TSSOP14: t.b. M24256 SCL 7 8 SDA AI02388C M24256 AI03760 Value Unit –40 to 125 C –65 to 150 C 260 215 C t.b.c. –0.6 to 6.5 V –0.3 to 6.5 V 4000 V 200 V ...
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... The Write Control signal is used to enable (WC=V write instructions to the entire memory area. When ) for an I BUS V CC MASTER fc = 100kHz fc = 400kHz 100 1000 M24256-A . (Figure 3 indicates how the establish the CC SS (see Table disable (WC ...
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... M24256-A 2 Figure Bus Protocol SCL SDA START CONDITION 1 SCL MSB SDA START CONDITION 1 SCL MSB SDA unconnected, the WC input is internally read and write operations are allowed. IL When WC=1, Device Select and Address bytes are acknowledged, Data bytes are not acknowl- edged ...
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... E1 Table 4. Most Significant Byte b15 b14 b13 b12 Note: 1. b15 is treated as Don’t Care on the M24256-A series. th clock Table 5. Least Significant Byte The 8 bit is the RW bit. This is set to ‘1’ for read and ‘0’ for write operations match occurs on ...
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... M24256-A) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. Data starts to become overwritten (in a way not formally spec- ified in this data sheet) ...
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... During the internal write cycle, the SDA input is disabled internally, and the device does not re- spond to any requests. ACK ACK ACK BYTE ADDR BYTE ADDR DATA IN R/W ACK ACK ACK BYTE ADDR BYTE ADDR DATA IN 1 R/W ACK M24256-A ACK ACK DATA IN 2 AI01106B 7/20 ...
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... M24256-A Figure 7. Write Cycle Polling Flowchart using ACK NO First byte of instruction with already decoded by M24xxx NO ReSTART STOP Minimizing System Delays by Polling On ACK During the internal write cycle, the memory discon- nects itself from the bus, and copies the data from its internal latches to the memory cells ...
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... In all read modes, the memory waits, after each byte read, for an acknowledgment during the 9 bit time. If the master does not pull the SDA line low during this time, the memory terminates the data transfer and switches to its stand-by state. M24256-A ACK NO ACK DATA OUT R/W ...
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... M24256-A Table 7. DC Characteristics (T = – 4 2 – 1 Symbol Parameter Input Leakage Current I LI (SCL, SDA) I Output Leakage Current LO -W series: I Supply Current CC -R series: Supply Current -W series: I CC1 (Stand-by) -R series: V Input Low Voltage (SCL, SDA) ...
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... Figure 9. AC Testing Input Output Waveforms M24256-A V =1 Unit 4 T =– Max Min Max 300 1000 ns 300 300 ns 300 20 1000 ns 300 20 300 ns 4700 ...
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... M24256-A Figure 10. AC Waveforms SCL SDA IN tCHDX START CONDITION SCL tCLQV SDA OUT SCL SDA IN tCHDH STOP CONDITION 12/20 tCHCL tCLCH tDLCL tDXCX tCLDX SDA SDA INPUT CHANGE tCLQX DATA VALID DATA OUTPUT tW tCHDX WRITE CYCLE tCHDH tDHDL STOP & BUS FREE ...
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... 3.6 V Note: 1. SBGA7 package available only for the “M24256 T” ORDERING INFORMATION Devices are shipped from the factory with the memory content set at all 1s (FFh). The notation used for the device number is as shown in Table 11. For a list of available options (speed, package, etc ...
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... M24256-A Table 12. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame Symb. Typ 7. 2. Figure 11. PSDIP8 (BN Note: 1. Drawing is not to scale. 14/20 mm Min. Max. Typ. 3.90 5.90 0.49 – 3.30 5.30 0.36 0.56 1.15 1.65 0.20 0.36 9.20 9.90 – – 0.300 6.00 6.70 – – 0.100 7.80 – 10.00 3.00 3. ...
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... Note: 1. Drawing is not to scale. mm Min. Max. Typ. 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 – – 0.050 5.80 6.20 0.25 0.50 0. M24256-A inches Min. Max. 0.053 0.069 0.004 0.010 0.013 0.020 0.007 0.010 0.189 0.197 0.150 0.157 – – 0.228 0.244 0.010 0.020 0.016 0.035 0.004 C L 15/20 ...
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... M24256-A Table 14. SO8 - 8 lead Plastic Small Outline, 200 mils body width Symb. Typ 0. 1. Figure 13. SO8 wide (MW SO-b Note: 1. Drawing is not to scale. 16/20 mm Min. Max. Typ. 2.03 0.10 0.25 1.78 0.35 0.45 – – 0.008 5.15 5.35 5.20 5.40 – – 0.050 7.70 8.10 0. ...
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... Note: 1. Drawing is not to scale. mm Min. Max. Typ. 1.10 0.05 0.15 0.85 0.95 0.19 0.30 0.09 0.20 4.90 5.10 6.25 6.50 4.30 4.50 – – 0.026 0.50 0. 0.08 DIE M24256-A inches Min. Max. 0.043 0.002 0.006 0.033 0.037 0.007 0.012 0.004 0.008 0.193 0.197 0.246 0.256 0.169 0.177 – – 0.020 0.028 0.003 C L TSSOP 17/20 ...
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... M24256-A Table 16. SBGA7 - 7 ball Shell Ball Grid Array Symb. Typ. A 0.430 A1 0.180 b 0.350 D 3.555 1 1.000 D2 E 2.275 FD 1.278 FE 0.388 N Note ball is closer than D2 to any other ball, thus giving an arrangement of equilateral triangles in which D2 3xD2 3xD2 3xD2/2 Figure 15. SBGA7 (EA) – Underside view (ball side) D BALL ” ...
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... Table 17. Revision History Date SBGA7(EA) package added OrderInfo, PackageData 17-Apr-2000 E1 and E0 are specified as having to be tied either to V Description of Revision M24256-A 19/20 ...
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... M24256-A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...