M24256-A STMicroelectronics, M24256-A Datasheet - Page 6

• Manufacturer Part Number: M24256-A
• Description: 256 Kbit Serial I C Bus EEPROM With Two Chip Enable Lines
• Manufacturer: STMicroelectronics

M24256-A
Figure 5. Write Mode Sequences with WC=1 (data write inhibited)
sponds to each address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC=1 (during a period of time from the START
condition until the end of the two address bytes)
will not modify the memory contents, and the ac-
companying data bytes will not be acknowledged,
as shown in Figure 5.
Byte Write
In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed location is write
protected by the WC pin, the memory replies with
a NoAck, and the location is not modified. If, in-
stead, the WC pin has been held at 0, as shown in
Figure 6, the memory replies with an Ack. The
master terminates the transfer by generating a
STOP condition.
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WC
BYTE WRITE
WC
PAGE WRITE
WC (cont’d)
PAGE WRITE
(cont’d)
NO ACK
DEV SEL
DEV SEL
DATA IN N
R/W
R/W
ACK
ACK
NO ACK
BYTE ADDR
BYTE ADDR
ACK
ACK
BYTE ADDR
BYTE ADDR
Page Write
The Page Write mode allows up to 64 bytes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
that is the most significant memory address bits
(b14-b6 for the M24256-A) are the same. If more
bytes are sent than will fit up to the end of the row,
a condition known as ‘roll-over’ occurs. Data starts
to become overwritten (in a way not formally spec-
ified in this data sheet).
The master sends from one up to 64 bytes of data,
each of which is acknowledged by the memory if
the WC pin is low. If the WC pin is high, the con-
tents of the addressed memory location are not
modified, and each data byte is followed by a
NoAck. After each byte is transferred, the internal
byte address counter (the 6 least significant bits
only) is incremented. The transfer is terminated by
the master generating a STOP condition.
When the master generates a STOP condition im-
mediately after the Ack bit (in the “10
ACK
ACK
DATA IN 1
DATA IN
NO ACK
NO ACK
DATA IN 2
AI01120B
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bit” time