AT49F8192 ATMEL Corporation, AT49F8192 Datasheet - Page 4

• Manufacturer Part Number: AT49F8192
• Description: 8-Megabit 512K x 16 5-volt Only CMOS Flash Memory
• Manufacturer: ATMEL Corporation

will be read. Examining the toggle bit may begin at any time
during a program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F8192 in
the following ways: (a) V
(typical), the program function is inhibited. (b) V
on delay: once V
Command Definition (in Hex)
Notes:
Absolute Maximum Ratings*
4
Read
Chip Erase
Sector
Erase
Word
Program
Boot Block
Lockout
Product ID
Entry
Product ID
Exit
Product ID
Exit
Temperature Under Bias ................................ -55 C to +125 C
Storage Temperature ..................................... -65 C to +150 C
All Input Voltages (including NC pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground ......................... -0.6V to V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
Command
Sequence
(3)
(3)
2. The 8K word boot sector has the address range
3. Either one of the Product ID Exit commands can be
4. SA = sector addresses:
1. The DATA FORMAT in each bus cycle is as follows:
(2)
AT49F8192/8192T
I/O15 - I/O8 (Don't Care); I/O7 - I/O0 (Hex)
00000H to 01FFFH for the AT49F8192 and 7E000H
to 7FFFFH for the AT49F8192T.
used.
For the AT49F8192
SA = 03XXX for PARAMETER BLOCK 1
SA = 05XXX for PARAMETER BLOCK 2
SA = 7FXXX for MAIN MEMORY ARRAY
Cycles
Bus
1
6
6
4
6
3
3
1
CC
has reached the V
5555
5555
5555
5555
5555
5555
Addr
Addr
xxxx
CC
1st Bus
Cycle
sense: if V
D
Data
AA
AA
AA
AA
AA
AA
F0
OUT
CC
2AAA
2AAA
2AAA
2AAA
2AAA
2AAA
CC
Addr
sense level, the
2nd Bus
(1)
Cycle
is below 3.8V
CC
CC
Data
to +0.6V
55
55
55
55
55
55
power
5555
5555
5555
5555
5555
5555
Addr
3rd Bus
Cycle
device will automatically time out 10 ms (typical) before
programming. (c) Program inhibit: holding any one of OE
low, CE high or WE high inhibits program cycles. (d) Noise
filter: pulses of less than 15 ns (typical) on the WE or CE
inputs will not initiate a program cycle.
*NOTICE:
Data
A0
F0
80
80
80
90
5. When the boot block programming lockout feature is
5555
5555
5555
Addr
Addr
For the AT49F8192T
SA = 7DXXX for PARAMETER BLOCK 1
SA = 7BXXX for PARAMETER BLOCK 2
SA = 79XXX for MAIN MEMORY ARRAY
not enabled, the boot block and the main memory
block will erase together (form the same sector erase
command). Once the boot region has been pro-
tected, only the main memory array sector will erase
when its sector erase command is issued.
4th Bus
Cycle
Stresses beyong those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Data
D
AA
AA
AA
IN
2AAA
2AAA
2AAA
Addr
5th Bus
Cycle
Data
55
55
55
SA
5555
5555
Addr
(4)(5)
6th Bus
Cycle
Data
30
10
40