M36W432BG ST Microelectronics, M36W432BG Datasheet
M36W432BG
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M36W432BG Summary of contents
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... PPF ACCESS TIME: 70ns, 85ns LOW POWER CONSUMPTION ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Top Device Code, M36W432TG: 88BAh – Bottom Device Code, M36W432BG: 88BBh FLASH MEMORY MEMORY BLOCKS – Parameter Blocks (Top or Bottom Location) – Main Blocks PROGRAMMING TIME – ...
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... M36W432TG, M36W432BG TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. LFBGA Connections (Top view through package SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Address Inputs (A0-A17 Address Inputs (A18-A20 Data Input/Output (DQ0-DQ15 Flash Chip Enable (EF Flash Output Enable (GF Flash Write Enable (WF Flash Write Protect (WPF) ...
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... Table 14. Flash Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 15. Flash Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . 28 FLASH BLOCK LOCKING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 16. Flash Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 17. Flash Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 M36W432TG, M36W432BG 3/66 ...
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... Figure 23. SRAM Write Cycle Waveform, UBS and LBS Controlled, GS Low . . . . . . . . . . . . . 45 Table 24. SRAM Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 24. SRAM Low V Table 25. SRAM Low V APPENDIX A. FLASH BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 26. Top Boot Block Addresses, M36W432TG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 27. Bottom Boot Block Addresses, M36W432BG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4/66 Data Retention AC Waveforms, E1 DDS Data Retention Characteristic DDS ...
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... Figure 30. Erase Suspend & Resume Flowchart and Pseudo Code Figure 31. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 APPENDIX D. FLASH COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE. 63 Table 34. Write State Machine Current/Next, sheet Table 35. Write State Machine Current/Next, sheet REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 36. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 M36W432TG, M36W432BG 5/66 ...
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... M36W432TG, M36W432BG SUMMARY DESCRIPTION The M36W432TG is a low voltage Multiple Memo- ry Product which combines two memory devices Mbit boot block Flash memory and a 4 Mbit SRAM. Recommended operating conditions do not allow both the Flash and SRAM devices to be active at the same time. ...
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... Figure 3. LFBGA Connections (Top view through package) M36W432TG, M36W432BG 7/66 ...
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... M36W432TG, M36W432BG SIGNAL DESCRIPTION See Figure 2 Logic Diagram and Table 1,Signal Names, for a brief overview of the signals connect this device. Address Inputs (A0-A17). Addresses are common inputs for the Flash and the SRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations ...
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... Note: Each device in a system should have DDQF pacitor close to the pin. See Figure 9, AC and V are the SSS Measurement Load Circuit. The PCB trace widths should be sufficient to carry the re- quired V M36W432TG, M36W432BG and V decoupled with a 0.1µF ca- PPF program and erase currents. PPF D- 9/66 ...
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... M36W432TG, M36W432BG FUNCTIONAL DESCRIPTION The Flash and SRAM components have separate power supplies and grounds and are distinguished by three chip enable inputs ory and, E1 and E2 for the SRAM Recommended operating conditions do not allow both the Flash and the SRAM active mode at the same time ...
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... 12V ± 5%. M36W432TG, M36W432BG DQ15-DQ8 DQ7-DQ0 Data Output Data Input Data out Word Read Data out ...
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... M36W432TG, M36W432BG MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause per- manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- Table 3 ...
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... DDQF V /2 DDQF Figure 6. AC Measurement Load Circuit V DDQ /2 V DDQF V DDF AI90166 0.1µF 0.1µ includes JIG capacitance Test Condition Typ V = 0V, f=1 MHz 0V, f=1 MHz OUT M36W432TG, M36W432BG summarized in Table Flash Memory 70/85 Units Min Max 2.7 3.3 V 2.7 3.3 V – ° ...
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... M36W432TG, M36W432BG Table 6. DC Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current Standby Current DDS DD I Supply Current (Reset) DDD I Supply Current DD I Supply Current (Read) DDR I Supply Current (Program) DDW I Supply Current (Erase) DDE Supply Current I DDWES ...
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... V 2.7V DDQF DDS SRAM Flash and DDQF DDS DD SRAM I = 100µ Flash & DDQF DDS DD SRAM I = –100µA OH Flash Flash Flash Flash M36W432TG, M36W432BG Min Typ Max –0.3 0.8 0.7 V DDQF V +0.3 DDQF min 0.1 min V DDQF –0.1 1.65 3.6 11.4 12 Unit ...
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... M36W432TG, M36W432BG PACKAGE MECHANICAL Figure 7. Stacked LFBGA66 12x8mm, 8x8 ball array, 0.8mm pitch, Bottom View Package Outline BALL "A1" Note: Drawing is not to scale. Table 7. Stacked LFBGA66 12x8mm, 8x8 ball array, 0.8mm pitch, Package Mechanical Data Symbol Typ A A1 ...
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... Figure 8. Stacked LFBGA66 Daisy Chain - Package Connections (Top view through package) M36W432TG, M36W432BG 17/66 ...
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... M36W432TG, M36W432BG Figure 9. Stacked LFBGA66 Daisy Chain - PCB Connections proposal (Top view through package) 18/66 ...
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... LFBGA66 8mm, 0.8mm pitch Option T = Tape & Reel Packing For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. M36 2.7V to 3.3V DDQF M36W432TG M36W432TG, M36W432BG -ZA T 19/66 ...
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... Blocks of 4 KWords and 63 Main Blocks of 32 KWords. The M36W432TG has the Parameter Blocks at the top of the memory address space while the M36W432BG locates the Parameter Blocks starting from the bottom. The memory maps are shown in Figure 10, Block Addresses. The Flash Memory features an instant, individual ...
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... KWord Blocks 00FFFF 008000 007FFF Total of 63 007000 32 KWord Blocks 000FFF 000000 PROTECTION REGISTER User Programmable OTP Unique device number (1) Protection Register Lock 2 1 M36W432TG, M36W432BG 32 KWords 32 KWords Total KWord Blocks 32 KWords 4 KWords Total KWord Blocks 4 KWords AI90164 0 AI07927 21/66 ...
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... M36W432TG, M36W432BG FLASH BUS OPERATIONS There are six standard bus operations that control the device. These are Bus Read, Bus Write, Out- put Disable, Standby, Automatic Standby and Re- set. See Table 2, Main Operation Modes, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations ...
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... Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write cycles are required to issue the command. The first bus cycle sets up the Erase command. M36W432TG, M36W432BG Command 23/66 ...
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... M36W432TG, M36W432BG The second latches the block address in the internal state machine and starts the Program/ Erase Controller. If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits b4 and b5 are set and the command aborts. Erase aborts if Reset turns to V cannot be guaranteed when the Erase operation is aborted, the block must be erased again ...
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... Read operations output the Status Register con- tent after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register (see Figure 11, M36W432TG, M36W432BG Protection Register Memory Map). Attempting to program a previously protected Protection Regis- ter will result in a Status Register error. The pro- tection of the Protection Register is not reversible ...
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... M36W432TG, M36W432BG The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on Table 11. Flash Commands Commands 1st Cycle Op. Add Data Read Memory 1+ Write X Array ...
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... OTP data 89h Don’t Care OTP data 8Ah Don’t Care OTP data 8Bh Don’t Care OTP data 8Ch Don’t Care OTP data M36W432TG, M36W432BG A2-A7 A8-A20 DQ0-DQ7 0 Don’t Care 20h 0 Don’t Care BAh 0 Don’t Care BBh ...
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... M36W432TG, M36W432BG Table 15. Flash Program, Erase Times and Program/Erase Endurance Cycles Parameter Word Program Double Word Program Quadruple Word Program Main Block Program Parameter Block Program Main Block Erase Parameter Block Erase Program/Erase Cycles (per Block) Note: 1. Typical time to program a Main or Parameter Block using the Double Word Program and the Quadruple Word Program commands respectively ...
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... Locked state after a hardware reset or when the device is powered-down. The status of an unlocked block can be changed to Locked or Locked-Down using the appropriate M36W432TG, M36W432BG software commands. A locked block can be un- locked by issuing the Unlock command. Lock-Down State Blocks that are Locked-Down (state (0,1,x))are ...
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... M36W432TG, M36W432BG Table 16. Flash Block Lock Status Item Block Lock Configuration Block is Unlocked Block is Locked Block is Locked-Down Table 17. Flash Protection Status Current (1) Protection Status (WP , DQ1, DQ0) F Program/Erase Current State Allowed 1,0,0 yes (2) no 1,0,1 1,1,0 yes 1,1,1 no 0,0,0 yes (2) no 0,0,1 0,1,1 no Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read in the Read Electronic Signature command with ...
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... When the Program Suspend Status bit is High (set to ‘1’), a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Re- sume command. The Program Suspend Status M36W432TG, M36W432BG Status bit can be PPF becomes invalid during an operation. PPF Status bit is Low (set to ‘ ...
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... M36W432TG, M36W432BG should only be considered valid when the Pro- gram/Erase Controller Status bit is High (Program/ Erase Controller inactive). Bit 2 is set within 5µs of the Program/Erase Suspend command being is- sued therefore the memory may still complete the operation rather than entering the Suspend mode. ...
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... F ELQV tAVAV VALID tAVQV tELQV tELQX tGLQV tGLQX VALID OUTPUTS DATA VALID ENABLED Parameter - t after the falling edge of E without increasing t GLQV F M36W432TG, M36W432BG tAXQX tEHQX tEHQZ tGHQX tGHQZ STANDBY AI07928 Flash 70 85 Min 70 85 Max 70 85 Min 0 0 ...
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... M36W432TG, M36W432BG Figure 13. Flash Write AC Waveforms, Write Enable Controlled 34/66 ...
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... Applicable seen as a logic input (V PPF Parameter Min Min Min Min Min V Low Min PPF Min Min Min Min Min Min Min Min Min Min < 3.6V). PPF M36W432TG, M36W432BG Flash Unit ...
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... M36W432TG, M36W432BG Figure 14. Flash Write AC Waveforms, Chip Enable Controlled 36/66 ...
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... Write Enable Low to Chip Enable Low WLEL CS t Write Protect High to Chip Enable High WPHEH Note: 1. Sampled only, not 100% tested. 2. Applicable seen as a logic input (V PPF Parameter Low PPF < 3.6V). PPF M36W432TG, M36W432BG Flash Unit 70 85 Min 70 85 Min 45 45 Min 45 45 Min ...
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... M36W432TG, M36W432BG Figure 15. Flash Power-Up and Reset AC Waveforms tVDHPH DDF DDQF Table 22. Flash Power-Up and Reset AC Characteristics Symbol t PHWL Reset High to Write Enable Low, Chip Enable t PHEL Low, Output Enable Low t PHGL (1,2) Reset Low to Reset High ...
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... Figure 16. SRAM Logic Diagram A0-A10 ory operations can be performed using a single low voltage supply, 2.7V to 3.3V, which is the same as the Flash voltage supply. DATA IN DRIVERS 256Kb x 16 RAM Array 2048 x 2048 COLUMN DECODER A11-A17 POWER-DOWN CIRCUIT M36W432TG, M36W432BG DQ0-DQ7 DQ8-DQ15 ...
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... M36W432TG, M36W432BG SRAM OPERATIONS There are five standard operations that control the SRAM component. These are Bus Read, Bus Write, Standby/Power-down, Data Retention and Output Disable. A summary is shown in Table 2, Main Operation Modes Read. Read operations are used to output the contents of the SRAM Array. The SRAM is in Read ...
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... VALID tAVQV tAXQX DATA VALID and/ High High Controlled S tAVAV VALID tE1LQV tE1LQX tE2HQV tE2HQX tBLQV tBLQX tGLQV tGLQX , UB S tPU 50% M36W432TG, M36W432BG DATA VALID AI07942 tE1HQZ tE2LQZ tBHQZ tGHQZ DATA VALID AI07943 and LB going Low tPD AI07913 41/66 ...
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... M36W432TG, M36W432BG Table 23. SRAM Read AC Characteristics Symbol Alt t t Read Cycle Time AVAV Address Valid to Output Valid AVQV ACC t t Address Transition to Output Transition AXQX BHQZ BHZ BLQV BLQX BLZ S t E1LQV t Chip Enable 1 Low or Chip Enable 2 High to Output Valid ...
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... The I/O pins are in output mode and input signals must not be applied. Controlled S tAVAV VALID tAVWH tE1LWH tE2HWH tAVWL tWLWH tBLWH tDVWH Note 2 must be asserted to initiate a write cycle. Output Enable (G are deasserted at the same time, DQ0-DQ15 remain high impedance. S M36W432TG, M36W432BG tWHAX tWHDZ INPUT VALID ) = Low (otherwise, DQ0-DQ15 are high S AI07944 43/66 ...
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... M36W432TG, M36W432BG Figure 21. SRAM Write AC Waveforms, E1 A0-A17 tGHQZ DQ0-DQ15 Note and/ impedance and and W are deasserted at the same time, DQ0-DQ15 remain high impedance The I/O pins are in output mode and input signals must not be applied. ...
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... DQ0-DQ15 remain high impedance Controlled with G S tAVAV VALID tAVWH tE1LWH tE2HWH tBLWH tWLWH tWLQZ tDVWH and LB Controlled tAVAV VALID tAVBH tE1LBH tE2HBH tAVBL tBLBH tWLBH tDVBH M36W432TG, M36W432BG Low S tWHAX tWHQX tWHDZ INPUT VALID AI07946 Low S tBHAX tBHDZ INPUT VALID AI07947 45/66 ...
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... M36W432TG, M36W432BG Table 24. SRAM Write AC Characteristics Symbol Alt t t Write Cycle Time AVAV AVE1L t , AVE2H t Address Valid to Beginning of Write AS t AVWL, t AVBL t , Address Valid to Chip Enable 1 Low or Chip Enable 2 AVE1H High AVE2L t t Address Valid to Write Enable High AVWH ...
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... Chip Disable to Power Down CDR t Operation Recovery Time R 2. Sampled only. Not 100% tested. Data Retention AC Waveforms, E1 DATA RETENTION MODE V DDS (min) tCDR Test Condition V = 1.5V, E1 DDS V V – 0. DDS M36W432TG, M36W432BG Controlled DDS (min) tR Min Typ V – 0.2V, S DDS 3 0.2V IN 1.5 ...
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... M36W432TG, M36W432BG APPENDIX A. FLASH BLOCK ADDRESS TABLES Table 26. Top Boot Block Addresses, M36W432TG Size # Address Range (KWord 1FF000-1FFFFF 1 4 1FE000-1FEFFF 2 4 1FD000-1FDFFF 3 4 1FC000-1FCFFF 4 4 1FB000-1FBFFF 5 4 1FA000-1FAFFF 6 4 1F9000-1F9FFF 7 4 1F8000-1F8FFF 8 32 1F0000-1F7FFF 9 32 1E8000-1EFFFF 10 32 1E0000-1E7FFF 11 32 1D8000-1DFFFF ...
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... M36W432TG, M36W432BG 36 32 0E8000-0EFFFF 35 32 0E0000-0E7FFF 34 32 0D8000-0DFFFF 33 32 0D0000-0D7FFF 32 32 0C8000-0CFFFF 31 32 0C0000-0C7FFF 30 32 0B8000-0BFFFF 29 32 0B0000-0B7FFF 28 32 0A8000-0AFFFF 27 32 ...
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... M36W432TG, M36W432BG APPENDIX B. COMMON FLASH INTERFACE (CFI) The Common Flash Interface is a JEDEC ap- proved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory ...
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... BCD value in 100 mV bit HEX value in volts bit BCD value in 100 mV bit HEX value in volts bit BCD value in 100 times typical n times typical M36W432TG, M36W432BG µs n µ times typical n times typical Value 2.7V 3.6V 11.4V 12.6V 16µs 16µ 512µ ...
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... M36W432TG, M36W432BG Table 31. Device Geometry Definition Offset Word Data Mode 27h 0016h Device Size = 2 28h 0001h Flash Device Interface Code description 29h 0000h 2Ah 0003h Maximum number of bytes in multi-byte program or page = 2 2Bh 0000h Number of Erase Block Regions within the device. 2Ch ...
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... Lock/bytes JEDEC-plane physical high address n bit "n" such that 2 = factory pre-programmed bytes n bit "n" such that 2 = user programmable bytes M36W432TG, M36W432BG Value "P" "R" "I" "1" "0" Yes No Yes No) No ...
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... M36W432TG, M36W432BG Table 33. Security Code Area Offset Data 80h 00XX Protection Register Lock 81h XXXX 82h XXXX 64 bits: unique device number 83h XXXX 84h XXXX 85h XXXX 86h XXXX 87h XXXX 88h XXXX 128 bits: User Programmable OTP 89h XXXX 8Ah ...
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... Error (1, 2) error_handler ( ) ; Program if (status_register.b4==1) /*program error */ Error (1, 2) error_handler ( ) ; if (status_register.b1==1) /*program to protect block error */ Block Error (1, 2) error_handler ( ) ; } Invalid) and b4 (Program Error) can be made after each program operation or after PPF M36W432TG, M36W432BG or G must be toggled invalid error */ PPF AI07932 55/66 ...
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... M36W432TG, M36W432BG Figure 26. Double Word Program Flowchart and Pseudo Code Start Write 30h Write Address 1 & Data 1 (3) Write Address 2 & Data 2 (3) Read Status Register YES YES YES NO Program to Protected Block Error (1, 2) YES End Note: 1. Status check of b1 (Protected Block sequence ...
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... Program error_handler ( ) ; Error ( (status_register.b1==1) /*program to protect block error */ error_handler ( ) ; } Invalid) and b4 (Program Error) can be made after each program operation or after PPF M36W432TG, M36W432BG addressToProgram2, dataToProgram2, addressToProgram3, dataToProgram3, addressToProgram4, dataToProgram4) /*see note (3) */ /*see note (3) */ /*see note (3) */ /*see note (3) */ must be toggled*/ ...
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... M36W432TG, M36W432BG Figure 28. Program Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another address Write D0h Program Continues 58/66 program_suspend_command ( ) { Program Complete if (status_register.b2==0) /*program completed */ ...
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... PPF Error (1) error_handler ( ) ; if ( (status_register.b4==1) && (status_register.b5==1) ) Command /* command sequence error */ Sequence Error (1) error_handler ( ) ; if ( (status_register.b5== erase error */ Erase Error (1) error_handler ( ) ; Erase to Protected if (status_register.b1==1) /*program to protect block error */ Block Error (1) error_handler ( ) ; } M36W432TG, M36W432BG or G must be toggled invalid error */ PPF AI07936 59/66 ...
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... M36W432TG, M36W432BG Figure 30. Erase Suspend & Resume Flowchart and Pseudo Code Start Write B0h Write 70h Read Status Register YES YES Write FFh Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock Write D0h Erase Continues 60/66 erase_suspend_command ( ) { (status_register.b6==0) /*erase completed */ ...
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... NO error_handler () ; /*Check the locking state (see Read Block Signature table )*/ writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/ } M36W432TG, M36W432BG AI04364 61/66 ...
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... M36W432TG, M36W432BG Figure 32. Protection Register Program Flowchart and Pseudo Code Start Write C0h Write Address & Data Read Status Register YES YES YES NO Program to Protected YES End Note: 1. Status check of b1 (Protected Block sequence error is found, the Status Register must be cleared before further Program/Erase Controller operations. ...
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... Program Erase Sus Erase Setup Read Array (continue) Program Erase Sus Erase Setup Read Array (continue) Program Erase Setup Setup M36W432TG, M36W432BG Prog/Ers Prog/Ers Read Suspend Resume Status (B0h) (D0h) (70h) Read Array Read Sts. Read Read Array Status Read Read Array ...
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... M36W432TG, M36W432BG Table 35. Write State Machine Current/Next, sheet Current State Read Elect.Sg. (90h) Read Array Read Elect.Sg. Read CFI Query Read Status Read Elect.Sg. Read CFI Query Read Elect.Sg. Read Elect.Sg. Read CFI Query Read CFI Query Read Elect.Sg. Read CFI Query ...
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... REVISION HISTORY Table 36. Document Revision History Date Version 19-Nov-2002 1.0 First Issue M36W432TG, M36W432BG Revision Details 65/66 ...
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... M36W432TG, M36W432BG Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice ...