M36W432BG ST Microelectronics, M36W432BG Datasheet - Page 20

• Manufacturer Part Number: M36W432BG
• Description: 32 Mbit 2Mb x16 / Boot Block Flash Memory and 4 Mbit 256Kb x16 SRAM / Multiple Memory Product
• Manufacturer: ST Microelectronics

M36W432TG, M36W432BG
FLASH DEVICE
The M36W432TG contains one 32 Mbit Flash
memory. This section describes how to use the
FLASH SUMMARY DESCRIPTION
The Flash Memory is a 32 Mbit (2 Mbit x 16) device
that can be erased electrically at block level and
programmed in-system on a Word-by-Word basis.
These operations can be performed using a single
low voltage (2.7 to 3.6V) supply. V
drive the I/O pin down to 1.65V. An optional 12V
V
tomer programming.
The device features an asymmetrical blocked ar-
chitecture with an array of 71 blocks: 8 Parameter
Blocks of 4 KWords and 63 Main Blocks of 32
KWords. The M36W432TG has the Parameter
Blocks at the top of the memory address space
while the M36W432BG locates the Parameter
Blocks starting from the bottom. The memory
maps are shown in Figure 10, Block Addresses.
The Flash Memory features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have
three levels of protection. They can be locked and
locked-down individually preventing any acciden-
tal programming or erasure. There is an additional
hardware protection against program and erase.
When V
20/66
PPF
power supply is provided to speed up cus-
PPF
V
PPLK
all blocks are protected
DDQF
allows to
Flash device and all signals refer to the Flash de-
vice.
against program or erase. All blocks are locked at
Power Up.
Each block can be erased separately. Erase can
be suspended in order to perform either read or
program in any other block and then resumed.
Program can be suspended to read data in any
other block and then resumed. Each block can be
programmed and erased over 100,000 cycles.
The device includes a Protection Register to in-
crease the protection of a system design. The Pro-
tection Register is divided into two segments, the
first is a 64 bit area which contains a unique device
number written by ST, while the second is a 128 bit
area, one-time-programmable by the user. The
user programmable segment can be permanently
protected. Figure 11, shows the Protection Regis-
ter Memory Map.
Program and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards.