TE28F008B3xxx Intel, TE28F008B3xxx Datasheet - Page 13

• Manufacturer Part Number: TE28F008B3xxx
• Description: (TE28F Series) SMART 3 ADVANCED BOOT BLOCK 4-8-16-32-MBIT FLASH MEMORY FAMILY
• Manufacturer: Intel

3.1.1
The flash memory has four read modes available:
read array, read identifier, read status and read
query. These modes are accessible independent of
the V
command must be issued to the CUI to enter the
corresponding mode. Upon initial device power - up
or after exit from reset, the device automatically
defaults to read array mode.
CE# and OE# must be driven active to obtain data
at the outputs. CE# is the device selection control;
when active it enables the flash memory device.
OE# is the data output control and it drives the
selected memory data onto the I/O bus. For all read
modes, WE# and RP# must be at V
illustrates a read cycle.
3.1.2
With OE# at a logic - high level (V
outputs are disabled. Output pins are placed in a
high - impedance state.
3.1.3
Deselecting the device by bringing CE# to a logic -
high level (V
which
consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a
high-impedance state independent of OE#. If
deselected during program or erase operation, the
device continues to consume active power until the
program or erase operation is complete.
3.1.4
From read mode, RP# at V
deselects the memory, places output drivers in a
high - impedance state, and turns off all internal
circuits. After return from reset, a time t
required until the initial read access outputs are
valid. A delay (t
return from reset before a write can be initiated.
After this wake - up interval, normal operation is
restored. The CUI resets to read array mode, and
the status register is set to 80H. This case is shown
in Figure 9A.
PRELIMINARY
PP
substantially
voltage. The appropriate Read Mode
READ
OUTPUT DISABLE
STANDBY
DEEP POWER-DOWN / RESET
IH
) places the device in standby mode,
PHWL
or t
reduces
PHEL
) is required after
IL
device
for time t
IH
), the device
IH
. Figure 7
PHQV
power
PLPH
is
If RP# is taken low for time t
or erase operation, the operation will be aborted
and the memory contents at the aborted location
(for a program) or block (for an erase) are no longer
valid, since the data may be partially erased or
written. The abort process goes through the
following sequence: When RP# goes low, the
device shuts down the operation in progress, a
process which takes time t
this time t
array mode (if RP# has gone high during t
Figure 9B) or enter reset mode (if RP# is still logic
low after t
returning from an aborted operation, the relevant
time t
read or write operation is initiated, as discussed in
the previous paragraph. However, in this case,
these delays are referenced to the end of t
rather than when RP# goes high.
As with any automated device, it is important to
assert RP# during system reset. When the system
comes out of reset, processor expects to read from
the flash memory. Automated flash memories
provide status information when read during
program or block erase operations. If a CPU reset
occurs with no flash memory reset, proper CPU
initialization may not occur because the flash
memory may be providing status information
instead of array data. Intel’s Flash memories allow
proper CPU initialization following a system reset
through the use of the RP# input. In this application,
RP# is controlled by the same RESET# signal that
resets the system CPU.
3.1.5
A write takes place when both CE# and WE# are
low and OE# is high. Commands are written to the
Command User Interface (CUI) using standard
microprocessor write timings to control flash
operations.
addressable memory location. The address and
data buses are latched on the rising edge of the
second WE# or CE# pulse, whichever occurs first.
Figure 8 illustrates a program and erase operation.
The available commands are shown in Table 6, and
Appendix A provides detailed information on
moving between the different modes of operation
using CUI commands.
PHQV
SMART 3 ADVANCED BOOT BLOCK
PLRH
PLRH
WRITE
or t
The
PHWL
, the part will either reset to read
, Figure 9C). In both cases, after
/t
CUI
PHEL
must be waited before a
does
PLRH
PLPH
to complete. After
not
during a program
occupy
PLRH
PLRH
13
an
,