X28C010 Xicor, X28C010 Datasheet - Page 3

• Manufacturer Part Number: X28C010
• Description: 5 Volt/ Byte Alterable E2PROM
• Manufacturer: Xicor

X28C010
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either OE or
CE is HIGH.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28C010 supports both a
CE and WE controlled write cycle. That is, the address
is latched by the falling edge of either CE or WE, which-
ever occurs last. Similarly, the data is latched internally by
the rising edge of either CE or WE, whichever occurs first.
A byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
Page Write Operation
The page write feature of the X28C010 allows the entire
memory to be written in 5 seconds. Page write allows
two to two hundred fifty-six bytes of data to be consecu-
tively written to the X28C010 prior to the commence-
ment of the internal programming cycle. The host can
fetch data from another device within the system during
a page write operation (change the source address), but
the page address (A
valid write cycle to the part during this operation must be
the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to two hundred fifty six bytes
in the same manner as the first byte was written. Each
successive byte load cycle, started by the WE HIGH to
LOW transition, must begin within 100 s of the falling
edge of the preceding WE. If a subsequent WE HIGH to
LOW transition is not detected within 100 s, the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continues to access the device within the byte load cycle
time of 100 s.
8
through A
16
) for each subsequent
3
Write Operation Status Bits
The X28C010 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
DATA Polling (I/O
The X28C010 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a simple
bit test operation to determine the status of the X28C010,
eliminating additional interrupt inputs or external hard-
ware. During the internal programming cycle, any at-
tempt to read the last byte written will produce the
complement of that data on I/O
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O
X28C010 is in the protected state and an illegal write
operation is attempted DATA Polling will not operate.
Toggle Bit (I/O
The X28C010 also provides another method for deter-
mining when the internal write cycle is complete. During
the internal programming cycle, I/O
HIGH to LOW and LOW to HIGH on subsequent at-
tempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
I/O
DP
TB
6
)
7
)
5
7
will reflect true data. Note: If the
4
RESERVED
TOGGLE BIT
DATA POLLING
7
3
(i.e., write data = 0xxx
2
6
will toggle from
1
3858 FHD F11
0