LM2640MTC-ADJ National Semiconductor, LM2640MTC-ADJ Datasheet - Page 12

• Manufacturer Part Number: LM2640MTC-ADJ
• Description: Dual Adjustable Step-Down Switching Power Supply Controller
• Manufacturer: National Semiconductor

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Theory of Operation
Basic Operation of the Current-Mode Controller
The output voltage is held at a constant value by the main
control loop, which is made up of the error amplifier , the
current sense amplifier , and the PWM comparator (refer to
the Block Diagram, Figure 3 ).
The LM2640 controller has two primary modes of operation:
Forced Pulse-Width Modulation (FPWM) where the control-
ler always operates at a fixed frequency, and Pulse-Skipping
mode where the controller frequency decreases at reduced
output loads to improve light-load efficiency.
FPWM Mode of Operation
Pulling the FPWM pin low initiates a mode of operation
called Forced Pulse-Width Modulation (FPWM). This means
that the LM2640 will always operate at a fixed frequency,
regardless of output load. The cycle of operation is:
The high-side FET switch turns ON at the beginning of every
clock cycle, causing current to flow through the inductor. The
inductor current ramps up, causing a voltage drop across the
sense resistor, and this voltage is amplified by the current
sense amplifier.
The voltage signal from the current sense amplifier is applied
to the input of the PWM comparator, where it is compared to
the control level set by the error amplifier. Once the current
sense signal reaches this control voltage, the PWM com-
parator resets the driver logic which turns OFF the high-side
FET switch.
The low-side FET switch turns on after a delay time which is
the lesser of either:
voltage is sensed by the shoot-through protection circuitry).
When operating at very light loads (in FPWM mode), the
inductor current must flow in a negative direction through the
low-side FET switch in order to maintain the fixed-frequency
mode of operation. For this reason, the built-in zero cross
detector is disabled when ever FPWM mode is activated
(that is, when ever the FPWM pin is pulled to a low state).
It should be noted that if the FPWM pin is high (operation
described in next section), the zero cross detector will turn
OFF the low-side FET switch anytime the inductor current
drops to zero (which prevents negative inductor current).
Pulse-Skipping Mode of Operation
Pulling the FPWM pin high allows the LM2640 to operate in
pulse-skipping mode at light loads, where the switching fre-
quency decreases as the output load is reduced. The con-
troller will operate in fixed-frequency mode, as described in
the previous section, if the output load current is sufficiently
high.
Pulse-skipping results in higher efficiency at light loads, as
decreasing the switching frequency reduces switching
losses. The load current value where the transition from
fixed-frequency to pulse-skipping operation occurs is the
point where the inductor current goes low enough to cause
the voltage measured across the current sense resistor (R4
or R13) to drop below 25 mV.
In pulse-skipping mode, the high-side FET switch will turn
ON at the beginning of the first clock cycle which occurs after
the voltage at the feedback pin falls below the reference
voltage. The high-side FET switch remains ON until the
voltage across the current sense resistor rises to 25 mV (and
then it turns OFF).
(a) The time it takes the SW pin voltage to reach zero (this
(b) 100 ns, which is the pre-set value for maximum delay.
12
Ramp Compensation
All current-mode controllers require the use of ramp com-
pensation to prevent subharmonic oscillations, and this com-
pensation is built into the LM2640. The internal compensa-
tion assumes an R
10 µH, and a maximum output voltage of 6V.
To prevent oscillations, the slope M of the compensation
ramp must be equal to the maximum downward slope of the
voltage waveform at the output of the current sense ampli-
fier. The relationship of the slope M to the external compo-
nents is given by:
M
Where:
M
M
age at the output of the current sense amplifier.
N is the gain of the current sense amplifier.
R
V
L is the inductance of the output inductor.
It is important to note that since the value R
the numerator and L is in the denominator, these two values
may be increased or decreased at the same ratio without
changing the slope.
At higher values of load current, a lower value R
selected. The inductance value for the output inductor
should be decreased by the same percentage to maintain
correct ramp compensation.
Application Information
Improved Transient Response
If the output voltage falls below 97% of the nominal value,
the low-voltage regulation (LREG) comparator will activate
logic which turns ON the high-side FET switch continuously
until the output returns to nominal. The low-side FET switch
is held OFF during this time.
This action will improve transient response since it bypasses
the error amplifier and PWM comparator, forcing the
high-side switch ON until the output returns to nominal. This
feature is disabled during start-up.
Boost High-Side Gate Drive
A “flying” bootstrap capacitor is used to generate the gate
drive voltage used for the high-side FET switch. This boot-
strap capacitor is charged up to about 5V using an internal
supply rail and diode when ever the low-side FET switch is
ON. When the high-side FET switch turns ON, the Source is
pulled up near the input voltage. The voltage across the
bootstrap capacitor boosts up the gate drive voltage, ensur-
ing that the Gate is driven at least 4.3V higher than the
Source.
Reference
The internal bandgap reference is used to generate a 2.5V
reference voltage which is connected to the REF pin. The
guaranteed tolerance of the REF voltage is
operating temperature range, as long as the current drawn is
A bypass capacitor on the REF pin is not required, but may
be used to reduce noise.
OUT
SENSE
COMP
COMP
CS AMP
5 mA.
(max) is the maximum output voltage.
is the slope of the compensation ramp.
= M
is the value of the current sense resistor.
(max) is the maximum downward slope of the volt-
CS AMP
SENSE
(max) = N X R
value of 25 m , inductor value of
SENSE
X V
SENSE
±
2% over the full
OUT
SENSE
appears in
(max) / L
will be