LM2640MTC-ADJ National Semiconductor, LM2640MTC-ADJ Datasheet - Page 14

• Manufacturer Part Number: LM2640MTC-ADJ
• Description: Dual Adjustable Step-Down Switching Power Supply Controller
• Manufacturer: National Semiconductor

www.national.com
Application Information
If the output voltage does not move to within −1% of nominal
in the period of 4096 counts, the device will latch OFF. To
restore operation, the power must be cycled OFF to ON.
Minimum Pulse Width
As the input voltage is increased, the pulse widths of the
switching FET’s decreases. If the pulse widths become nar-
rower than 350 ns, pulse jitter may occur as the pulses
alternate with slightly different pulse widths. This is does not
affect regulator stability or output voltage accuracy.
Start-Up Issues
The LM2641 contains an output undervoltage protection
circuit which is made up of a digital counter and a compara-
tor which monitors V
counting clock cycles when the input voltage reaches ap-
proximately 3V. If the counter reaches 4096 cycles before
the output voltage rises to within 1% of nominal value, the IC
will be latched off in an undervoltage fault condition.
The function of this protection is to shut the regulator off if the
output is overloaded (such as a short to ground). However,
the UV latch can cause start-up problems if the circuit is not
properly designed. The following two sections explain how to
avoid these types of problems:
Input Voltage Rise Time
If the input voltage rises too slowly, the LM2641 will latch off
in an undervoltage condition. To avoid this problem, the input
voltage must rise quickly enough to allow the output to get
into regulation before the 4096 count time interval elapses.
For a switching frequency of 300 kHz, 4096 cycles will be
completed in 13.6 milliseconds.
In reality, the total rise time of V
4096 clock cycle limit if reliable start-up is to be assured. It
should be noted that the total rise time of V
by current loading when the power converter begins switch-
ing (which draws power from the input capacitors) causing
their voltage to sag (details of input capacitor requirements
are outlined in the next section).
It is also important to note that this type of start-up problem
is more likely to occur at higher values of output voltage,
since the input voltage must rise to a higher voltage to allow
the output voltage to regulate (which means the input dV/dt
rate has to be faster). The recommended output voltage limit
of 6V should not be exceeded.
Input Capacitance
The amount and type of input capacitance present is directly
related to how well the regulator can start up. The reason is
that the input capacitors serve as the source of energy for
the power converter when the regulator begins switching.
Typically, the input voltage (which is the voltage across the
input capacitors) will sag as the power converter starts draw-
ing current which will cause a dip in V
If the input capacitors are too small or have excessive ESR,
the input volatge may not be able to come up fast enough to
allow the output volatge to get into regulation before the
digital clock counts off 4096 cycles and the part will latch off
as an undervoltage fault.
To prevent this type of start-up problem:
1. The input capacitors must provide sufficient bulk capaci-
tance and have low impedance. Solid Tantalum capaci-
tors designed for high-frequency switching applications
are recommended as they generally provide the best
OUT
. During turn-on, the counter begins
IN
should not approach the
IN
as it is ramping up.
(Continued)
IN
is also affected
14
2. The input capacitors must be physically located not
Loop Compensation
The LM2640 must be properly compensated to assure
stable operation and good transient response. As with any
control loop, best performance is achieved when the com-
pensation is optimized so that maximum bandwidth is ob-
tained while still maintaining sufficient phase margin for good
stability.
Best performance for the LM2640 is typically obtained when
the loop bandwidth (defined as the frequency where the loop
gain equals unity) is in the range of F
In the discussion of loop stability, it should be noted that
there is a high-frequency pole f
be approximated by:
f
Where:
As can be seen in the approximation for Q
frequency for f
The lowest frequency for f
V
As noted above, the location of the pole f
the range of about F
near the unity-gain crossover frequency, and it can signifi-
cantly reduce phase margin if left uncompensated. Fortu-
nately, the ESR of the output capacitor(s) forms a zero which
is usually very near the frequency of f
cancellation of the negative phase shift it would otherwise
cause. For this reason, the output capacitor must be care-
fully selected.
Most of the loop compensation for the LM2640 is set by an
R-C network from the output of the error amplifier to ground
(see Figure 4 ). Since this is a transconductance amplifier, it
has a very high output impedance (160 k ).
p
IN
(HF)
= 4.5V and V
cost/performance characteristics and maintain a very
low ESR even at cold temperatures. Ceramic capacitors
also have very low ESR over the full temperature range,
but X5R/X7R dielectric types should be used to assure
sufficient capacitance will be provided (Z5U or Y5F
types are not suitable).
more than one centimeter away from the switching
FET’s, as trace inductance in the switching current path
can cause problems.
Some of the newer electrolytic types such as POSCAP,
OSCON, and polymer electrolytic may also be usable as
input capacitors. However, care must be taken if the
application will be used at low temperatures as the ESR
of these capacitors may increase significantly at tem-
peratures below 0˚C. Most aluminum electrolytes are
not usable with this IC at temperatures below this limit.
Check the ESR specifications of the selected capacitor
carefully if low temperature operation will be required.
F
OSC
/2 X Q
p
(HF) occurs at the maximum value of V
OUT
OSC
S
= 1.8V).
(Assumes Q
/10 to F
p
(HF) is about F
p
OSC
(HF), whose frequency can
S
/4. This pole will often be
<
OSC
0.5)
p
(HF), and provides
p
/10 to F
(HF) is typically in
S
OSC
, the highest
/10 (when
OSC
/5.
IN
.