LM78 National Semiconductor, LM78 Datasheet - Page 7

• Manufacturer Part Number: LM78
• Description: Microprocessor System Hardware Monitor
• Manufacturer: National Semiconductor

ISA TIMING CHARACTERISTICS
f
t
t
t
t
ISA WRITE TIMING
t
t
t
SYSCLK
CS
CS
SA
SA
SDWR
SDWR
WR
The delay between consecutive IORD and IOWR pulses should be greater than 50 ns to ensure that an Power-on reset does not
occur unintentionally. (See Section 3.2 ‘Resets’ )
(setup)
(setup)
(setup)
(hold)
(hold)
AC Electrical Characteristics
+5.75 V
25˚C.
Symbol
(setup)
(hold)
DC
unless otherwise specified. Boldface limits apply for T
System Clock (SYSCLK) Input Frequency
CS Active to IORD/IOWR Active
IORD/IOWR Inactive to CS Inactive
Address Valid to IORD/IOWR Active
IORD/IOWR Inactive to Address Invalid
Data Valid to IOWR Active
IOWR Inactive to Data Invalid
IOWR Active to Rising Edge of SYSCLK
Parameter
FIGURE 1. ISA Bus Write Timing Diagram
(Note 13) The following specifications apply for +4.25 V
7
Conditions
A
= T
J
= T
MIN
to T
(Note 8)
Typical
MAX
8.33
; all other limits T
(Note 9)
Limits
10
10
30
10
20
5
5
DS012873-4
DC
A
V
= T
CC
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J
=
(Limits)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
Units
MHz