P89C660 Philips Semiconductors, P89C660 Datasheet - Page 61

• Manufacturer Part Number: P89C660
• Description: 80C51 8-bit Flash microcontroller family
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Expanded Data RAM Addressing
The P89C660/662/664/668 has internal data memory that is
mapped into four separate segments: the lower 128 bytes of RAM,
upper 128 bytes of RAM, 128 bytes Special Function Register (SFR),
and 256 bytes expanded RAM (ERAM) (256 bytes for the ’660; 768
bytes for the ’662; 1792 bytes for the ’664; 7936 bytes for the ’668).
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are
2. The Upper 128 bytes of RAM (addresses 80H to FFH) are
3. The Special Function Registers, SFRs, (addresses 80H to FFH)
4. The 256/768/1792/7936-bytes expanded RAM (ERAM,
The Lower 128 bytes can be accessed by either direct or indirect
addressing. The Upper 128 bytes can be accessed by indirect
addressing only. The Upper 128 bytes occupy the same address
space as the SFR. That means they have the same address, but are
physically separate from SFR space.
When an instruction accesses an internal location above address
7FH, the CPU knows whether the access is to the upper 128 bytes
of data RAM, or to SFR space by the addressing mode used in the
instruction. Instructions that use direct addressing, access SFR
space. For example:
accesses the SFR at location 0A0H (which is P2). Instructions that
use indirect addressing, access the Upper 128 bytes of data RAM.
2002 Oct 28
80C51 8-bit Flash microcontroller family
16KB/32KB/64KB ISP/IAP Flash with 512B/1KB/2KB/8KB RAM
MOV 0A0H,A
directly and indirectly addressable.
indirectly addressable only.
are directly addressable only.
00H – XFFH/2FFH/6FFH/1FFFH) are indirectly accessed by
move external instruction, MOVX, and with the EXTRAM bit
cleared, see Figure 53.
NOTE:
*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new
bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
AUXR
Symbol
AO
EXTRAM
—
Address = 8EH
Not Bit Addressable
Bit:
Function
Disable/Enable ALE
AO
0
1
Internal/External RAM access using MOVX @Ri/@DPTR
EXTRAM
0
1
Not implemented, reserved for future use*.
—
7
Operating Mode
ALE is emitted at a constant rate of
ALE is active only during off-chip memory access.
Operating Mode
Internal ERAM access using MOVX @Ri/@DPTR
External data memory access.
—
6
—
5
Figure 53. AUXR: Auxiliary Register
—
4
61
1
/
3
—
3
the oscillator frequency (6 clock mode;
address bits (the contents of DPL) with data. MOVX @Ri and MOVX
For example:
where R0 contains 0A0H, accesses the data byte at address 0A0H,
rather than P2 (whose address is 0A0H).
The ERAM can be accessed by indirect addressing, with EXTRAM
bit cleared and MOVX instructions. This part of memory is physically
located on-chip, logically occupies the first 256 bytes (660), 768
(662), 1792 (664), 7936 (668) of external data memory.
With EXTRAM = 0, the ERAM is indirectly addressed, using the
MOVX instruction in combination with any of the registers R0, R1 of
the selected bank or DPTR. An access to ERAM will not affect ports
P0, P3.6 (WR#) and P3.7 (RD#). P2 SFR is in output state during
external addressing. For example, with EXTRAM = 0,
where R0 contains 0A0H, access the ERAM at address 0A0H rather
than external memory. An access to external data memory locations
higher than the ERAM will be performed with the MOVX DPTR
instructions in the same way as in the standard 80C51 (with P0 and
P2 as data/address bus, and P3.6 and P3.7 as write and read timing
signals. Refer to Figure 54).
With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar
to the standard 80C51. MOVX @ Ri will provide an 8-bit address
multiplexed with data on Port 0 and any output port pins can be
used to output higher order address bits. This is to provide the
external paging capability. MOVX @DPTR will generate a 16-bit
address. Port 2 outputs the high-order eight address bits (the
contents of DPH) while Port 0 multiplexes the low-order eight
@DPTR will generate either read or write signals on P3.6 (WR) and
P3.7 (RD).
The stack pointer (SP) may be located anywhere in the 256 bytes
RAM (lower and upper RAM) internal data memory. The stack may
not be located in the ERAM.
MOV @R0,A
MOVX @R0,A
—
2
P89C660/P89C662/P89C664/
EXTRAM
1
AO
0
Reset Value = xxxx xx10B
1
/
6
f
OSC
in 12 clock mode)
P89C668
Product data
SU01711