MC9S12A256 Motorola, MC9S12A256 Datasheet - Page 81

• Manufacturer Part Number: MC9S12A256
• Description: MC9S12DT256 Device User Guide V03.03
• Manufacturer: Motorola

Section 6 HCS12 Core Block Description
6.1 CPU12 Block Description
Consult the CPU12 Reference Manual for information on the CPU.
When the CPU12 Reference Manual refers to cycles this is equivalent to Bus Clock Periods.
6.2 HCS12 Module Mapping Control (MMC) Block Description
Consult the MMC Block User Guide for information on the Module Mapping Control Block.
6.2.1 Device specific information
6.3 HCS12 Multiplexed External Bus Interface (MEBI) Block
Description
Consult the MEBI Block Guide for information on Multiplexed External Bus Interface.
6.3.1 Device specific information
6.4 HCS12 Interrupt (INT) Block description
Consult the INT Block guide for information on HCS12 Interrupt block.
6.5 HCS12 Background Debug (BDM) Block Description
Consult the BDM Block guide for information on HCS12 Background Debug block
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INITEE
– Reset state: $01
– Bits EE11-EE15 are writeable once in Normal and Emulation Mode
PPAGE
– Reset state : $00
– Register is writeable anytime in all modes
PUCR
– Reset State : $90
MC9S12DT256 Device User Guide — V03.03
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