MC912DG128A Motorola, MC912DG128A Datasheet - Page 243

• Manufacturer Part Number: MC912DG128A
• Description: Microcontrollers
• Manufacturer: Motorola

SP0SR — SPI Status Register
SP0BR — SPI Baud Rate Register
21-msi
MOTOROLA
RESET:
RESET:
SPIF
Bit 7
Bit 7
0
0
0
WCOL
6
0
0
6
0
Read anytime. Write anytime.
At reset, E Clock divided by 2 is selected.
SPR[2:0] — SPI Clock (SCK) Rate Select Bits
Read anytime. Write has no meaning or effect.
SPIF — SPI Interrupt Request
SPR2
These bits are used to specify the SPI clock rate.
SPIF is set after the eighth SCK cycle in a data transfer and it is
cleared by reading the SP0SR register (with SPIF set) followed by an
access (read or write) to the SPI data register.
0
0
0
0
1
1
1
1
5
0
0
5
0
0
SPR1
0
0
1
1
0
0
1
1
Multiple Serial Interface
MODF
Table 36 SPI Clock Rate Selection
SPR0
4
0
0
4
0
0
1
0
1
0
1
0
1
E Clock
Divisor
3
0
0
3
0
0
128
256
16
32
64
2
4
8
SPR2
2
0
2
0
0
E Clock = 4 MHz
Frequency at
62.5 kHz
31.3 kHz
15.6 kHz
2.0 MHz
1.0 MHz
500 kHz
250 kHz
125 kHz
Serial Peripheral Interface (SPI)
SPR1
MC68HC912DT128A Rev 2.0
1
0
1
0
0
Multiple Serial Interface
SPR0
Bit 0
Bit 0
E Clock = 8 MHz
0
0
0
Frequency at
62.5 KHz
31.3 KHz
500 KHz
250 KHz
125 KHz
4.0 MHz
2.0 MHz
1.0 MHz
$00D3
$00D2
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