M37754 Mitsubishi, M37754 Datasheet

Page 1

... I/O, A-D converter, D-A con- verter, and so on. The differences between M37754M8C-XXXGP, M37754M8C-XXXHP, M37754S4CGP and M37754S4CHP are listed in the table on the next page: the internal ROM, usable processor mode, and package. Therefore, the following descriptions will be for the M37754M8C- XXXGP unless otherwise noted ...

Page 2

... /INT /KI 100 Differences between M37754M8C-XXXGP, M37754M8C-XXXHP, M37754S4CGP, and M37754S4CHP Product Internal ROM M37754M8C-XXXGP M37754M8C-XXXHP M37754S4CGP Not equipped M37754S4CHP (External ROM) 2 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER M37754M8C-XXXHP or M37754S4CHP Outline 100P6Q-A Usable processor mode • ...

Page 3

... M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP Data Buffer DB (8) H Data Buffer DB (8) L Instruction Queue Buffer Q (8) 0 Instruction Queue Buffer Q (8) 1 Instruction Queue Buffer Q (8) 2 Incrementer(24) Program Address Register PA(24) Data Address Register DA(24) Incrementer/Decrementer(24) Program Counter PC(16) Program Bank Register PG(8) Data Bank Register DT(8) Input Buffer Register IB(16) ...

Page 4

... Input/Output characteristic Output current Memory expansion Operating temperature range Device structure Package Notes 1: The M37754S4CGP and the M37754S4CHP are not equipped with ROM. 2: Input/Output ports for the M37754S4CGP and the M37754S4CHP are as shown below : • P5-P8, P11 (8-bit 5) • P4 (5-bit 1) • P9 (6-bit 1) ...

Page 5

... Note impossible to change the input level of the BYTE pin in each bus cycle. In other words, bus width cannot be switched dynamically. Fix the input level of the BYTE pin to “H” or “L” according to the bus width used. M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Input/ Output Supply 5 V± ...

Page 6

... P11 – P11 0 7 I/O port P11 6 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Input/ Output I/O In single-chip mode, these pins have the same functions as port P0. In memory expansion mode or microprocessor mode, these pins become data I/O pins and operate as follows: (1) When using 16-bit width as external data bus width: • ...

Page 7

... BASIC FUNCTION BLOCKS The M37754M8C-XXXGP contains the following devices on a single chip: ROM, RAM, CPU, bus interface unit, timers, UART, A-D con- verter, D-A converter, I/O ports, clock generating circuit and others. Each of these devices is described below. MEMORY The memory map is shown in Figure 1. The address space is 16 ...

Page 8

... UART1 transmit/receive control register 1 00003D 00003E UART1 receive buffer register 00003F Fig. 2 Location of peripheral devices and interrupt control registers 8 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Address (Hexadecimal notation) Count start register 000040 000041 One-shot start register 000042 000043 ...

Page 9

... DT Data bank register DT Fig. 3 Register structure M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER In index addressing mode, register X is used as the index register and the contents of this address is added to obtain the real address. Index register X functions as a pointer register which indicates an address of data table in instructions MVP, MVN, RMPA (Repeat MultiPly and Accumulate) ...

Page 10

... Normally the low-order 8 bits of the direct page register (DPR) is set to “00 ” M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER PROCESSOR STATUS REGISTER (PS) Processor status register (PS 11-bit register. It consists of a flag to indicate the result of operation and CPU interrupt levels. Branch operations can be performed by testing the flags and N ...

Page 11

... CPU Fig. 4 Relationship between the CPU and the bus interface unit M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 9. Processor interrupt priority level (IPL) The processor interrupt priority level (IPL) consists of 3 bits and de- termines the priority of processor interrupts from level 0 to level 7. ...

Page 12

... Fig. 5 Basic waveforms of bus interface unit 12 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER __ (BYTE) to “L” (external data bus width = 16 bits). The internal memory area is always treated as 16-bit bus width regardless of BYTE. When performing 16-bit data read or write, if the conditions for simul- taneously accessing two bytes are not satisfied, waveforms (2) and (4) are used to access each byte, one by one ...

Page 13

... When data read or write is enabled, the bus interface unit performs data read or write. During data read, the CPU waits until the entire data is stored in the data buffer. The bus interface unit sends the address sent from the M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ___ MITSUBISHI MICROCOMPUTERS 13 ...

Page 14

... ADRS : Address R-D : Read data W-D : Write data Fig. 6 Bus cycle selection (low-speed running) 14 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Low-speed running ( 12 access ...

Page 15

... Note: Refer to internal memory access bus cycle select bit (bit 2 of processor mode register 0 ; Figure 14). ADRS : Address R-D : Read data W-D : Write data Fig. 7 Bus cycle selection (high-speed running) M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER High-speed running ( access Read ...

Page 16

... When the external data bus width is 8 bits, the function to output the low-order address from the Di pin while “H” can be selected only in special area access cycle. Refer to the section on the processor mode for details. Fig. 8 Output signals at 3- access in high-speed running 16 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER – – ...

Page 17

... Note: When Fig. 9 Processor mode register 1 bit configuration M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Processor mode register 1 5F These bits must be “00.” Clock source for peripheral devices select bit (Note CPU running speed select bit ...

Page 18

... Figure 15) is set to “1.” Fig. 10 Interrupt control register bit configuration 18 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 2. Interrupt types and the interrupt vector addresses ____ INT external interrupt ...

Page 19

... Table 4. M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The interrupt request bit and the interrupt priority level of each inter- rupt source are sampled and latched at each operation code fetch ...

Page 20

... Priority detection time Select one from with bits 4 and 5 of processor mode register 0 Fig. 13 Interrupt priority detection time 20 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 4. Value set in processor interrupt level (IPL) during an interrupt Interrupt types Reset ____ DBC ...

Page 21

... After bit 5 is set to “1” once, bit 5 cannot be cleared to “0” except external reset and software reset. 3: Bits 6 and 7 are write-only bits and undefined at read. Do not use SEB or CLB insturuction when setting bits 0–7. Fig. 15 Processor mode register 0 bit configuration M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 3 2 ...

Page 22

... OUT 0 ___ Fig. 16 INT /key input interrupt input circuit block diagram 3 22 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER pins is performed. 0 When using the above key input interrupt, select the edge sense __ . Figure 10 shows the which uses the falling edge from “H” to “L” with the INT 0 control register so that an interrupt request can occur by inputting “ ...

Page 23

... Note: Perform write and read to/from timer Ai register in the condition of 16-bit data length : data length flag (m) = “0”. Fig. 17 Block diagram of timer A M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (1) Timer mode [00] Figure 18 shows the bit configuration of the timer Ai mode register during timer mode. Bits 0 and 1 of the timer Ai mode register must be “ ...

Page 24

... Note: When selecting no gate function (bit 4 = “0”) in timer mode, fix bit 5 to “0”. Fig. 18 Timer Ai mode register bit configuration during timer mode 24 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER When bit 5 is “0, counting restarts from the value which is contained at restarting (gate function 0 [no reload]) and an overflow occurs ( cycles of the count source later. Figure 21 shows that operation. When bit 5 is “ ...

Page 25

... Bit 4 Bit Timer mode register Bit 4 Bit Fig. 20 Count waveform when gate function is available M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Count start register (Stop at “0”, Start at “1”) Timer A0 count start bit Timer A1 count start bit ...

Page 26

... IN Invalid level TAi interrupt request bit Fig. 22 Timer operation example with gate function 1 (reload) selected 26 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Count stop Cleared by accepting the interrupt request or by software Reloaded Reloaded duration Count stop Cleared by accepting the interrupt request or by software ...

Page 27

... OUT the output from the pin changes the count direction. Therefore, bit 4 must be “0” unless the output from the TAi OUT lect the count direction. M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER pin OUT pin. ...

Page 28

... Increment-count at each edge Fig. 26 Two-phase pulse processing operation of timer A4 28 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER be set to “1” and bits and 5 must be “0”. Bits 6 and 7 are ig- nored. Note that bits 5, 6, and 7 of the up-down register (44 the two-phase pulse signal processing select bits for timers A2, A3 and A4 respectively ...

Page 29

... The counter is reloaded with new data from the reload register at the next reload time. Undefined data is read when timer Ai is read. M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER pin. Soft ...

Page 30

... Fig. 30 Pulse output example when external rising edge is selected Selected clock source Pfi TAi IN (rising edge) TAi OUT Example when the contents of the reload register is 0004 Fig. 31 Example when trigger is re-issued during pulse output 30 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 16 16 MITSUBISHI MICROCOMPUTERS ...

Page 31

... The reload register and the counter are both divided into 8-bit halves. The low-order 8 bits function as a prescaler and the high-order 8 bits M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER function as the 8-bit length pulse width modulator. The prescaler counts the clock selected by bits 6 and 7. A pulse is generated ...

Page 32

... Fig. 34 8-bit length pulse width modulator output pulse example 32 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER high-order 8 bits of the reload register are m, the duration “H” of pulse is selected clock frequency And the output pulse period is ...

Page 33

... Note: Perform write and read to/from timer Bi register in the condition of 16-bit data length : data length flag (m) =“0”. Fig. 35 Timer B block diagram M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER As shown in Figure 19, the timer Bi count start bit is at the same ad- dress as the timer Ai count start bit ...

Page 34

... IN signal to the next fall as shown in Figure 40. 34 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Fig. 36 Timer Bi mode register bit configuration during timer mode ...

Page 35

... Fig. 39 Pulse period measurement mode operation (example of measuring the interval between the falling edge to next falling one) Selected clock source Pfi TBi IN Reload register counter Counter 0 Count start flag Interrupt request signal Fig. 40 Pulse width measurement mode operation M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER pin IN , which indicates that a 16 MITSUBISHI MICROCOMPUTERS 35 ...

Page 36

... A0 to A2’s one-shot pulses or their falling edge. Bit 6 of the waveform output mode register selects it. When that is “0”, both the rising and falling edges become the start trigger; when that is “1”, the falling edge becomes it. 36 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ...

Page 37

... Fig. 43 Three-phase waveform mode block diagram M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 37 ...

Page 38

... Do not select. Fig. 44 Bit configuration of pulse output data registers 1 and 0 in three-phase waveform mode 38 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ), the data is In the three-phase waveform mode, setting bit 7 of the waveform out- 16 put mode register (address 1A ( phases) and their negative waveforms ( phases) output from the respective ports. When that bit is “ ...

Page 39

... U-phase waveform output U-phase waveform output Fig. 45 U-phase waveform output example in three-phase mode 0 (triangular wave modulation) M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Then, write “1” to the U-phase output polarity set buffer (bit 1 at ad- dress 1C ) before the counter of timer B2 becomes 0000 ...

Page 40

... U-phase waveform output U-phase waveform output Fig. 47 U-phase waveform output example in three-phase mode 1 (triangular wave modulation) 40 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER After the procedure above, three-phase mode 1 starts operation when actuating the timer B2. When the counter of timer B2 becomes 0000 rupt request occurs and timer A2 simultaneously starts one-shot pulse output ...

Page 41

... The width of “L” level can be also modified by changing the value of timer B2, timer A2 or timer V-, W-phase waveform and V-, W-phase waveform, having their negative phase, are similarly output according to the corresponding timer operation. M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER , the timer MITSUBISHI MICROCOMPUTERS 41 ...

Page 42

... Fig.76) : Waveform output mode register (address 1A Fig. 48 Pulse output port mode block diagram 42 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Set timers A1 and A0 to the timer mode because they are used in the pulse output mode. Additionally, set bit 2 of the corresponding timer Ai mode register to “ ...

Page 43

... Fig.76). Fig. 49 Bit configuration of waveform output mode register in pulse output port mode M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pulse mode 0 Address This mode divides a pulse output port into 4 bits and 4 bits and indi- 16 vidually controls them ...

Page 44

... M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER The polarity select bit (bit 3) of waveform output mode register must be “0” to select the positive polarity. The other operations are the same as that of pulse mode 0 ...

Page 45

... RTP0 2 Fig. 53 Example waveforms in pulse mode 1 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pulse outpu port (RTP1) example Example of pulse width modulation for above pulse output port using timer A2 Pulse outpu port (RTP0) example in the case of polarity select bit = “1” ...

Page 46

... No sleep 1 : Sleep Fig. 55 UARTi Transmit/Receive mode register bit configuration 46 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (UART) serial I/O port using start and stop bits. Figures 56 and 57 show the connections of receiver/transmitter ac- cording to the mode. Figure 58 shows the bit configuration of the UARTi Transmit/Receive control register ...

Page 47

... MSB LSB EPTY SUM PER FER OER RI Fig. 58 UARTi Transmit/Receive control register bit configuration M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Data bus(odd) Data bus(even 8bit 9bit 9 bit Parity 7bit Synchronous ...

Page 48

... OER RI RE Fig. 59 Clock synchronous serial communication 48 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER transmission clock CLKj. Therefore, when the selected clock is Pfi, Bit Rate = Pf On the clock receiving side, the TCS Transmit/Receive control register 0 are ignored because an external clock is selected. ...

Page 49

... EPTY X j Fig. 60 Clock synchronous serial I/O timing M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER changes to “1” at the next cycle just after the T and changes to “0” when transmission starts. Therefore, this flag can ____ be used to determine whether data transmission has completed. ...

Page 50

... Note: It outputs “H” when bit 2 of the port P8 direction register is “1”, and it becomes floating when bit 2 is “0”. 50 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Receive Receive starts when bit 2 (REk flag) of UARTk Transmit/Receive control register 1 is set to “1”. ...

Page 51

... After bit 5 is set to “1” once, bit 5 cannot be cleared to “0” except external reset and software reset. 3: Bits 6 and 7 are write-only bits and undefined at read. Do not use SEB or CLB insturuction when setting bits 0–7. Fig. 63 Particular function select register 1 bit configuration M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1 0 ...

Page 52

... Fig. 64 Connection relation between transmit buffer register, receive buffer register, and data bus 52 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER transmit buffer register and the receive buffer register when writing transmit data to the transmit buffer register or reading receive data from the receive buffer register. Accordingly, the transmitter’ ...

Page 53

... EXT Bit 4 is the stop bit length select bit to select 1 stop bit or 2 stop bits. M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Bit select bit of odd parity or even parity. In the odd parity mode, the parity bit is adjusted so that the sum the data and parity bit is always odd ...

Page 54

... Fig. 66 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits selected 54 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Once transmission has started, the TEi flag, TIi flag, and CTSi signal ____ (if CTSi input is selected ) are ignored until data transmission is com- ____ pleted ...

Page 55

... Fig. 67 Receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit selected M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER to “0” when reading the low-order byte of the receive buffer register or when writing “0” to the REi flag or when setting to a parallel port. ...

Page 56

... AN /AD 7 TRG 0 f Clock source select bit (bit 6 of processor mode register 1) Fig. 68 A-D converter block diagram 56 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Vref Comparator function select register (0: A-D converter, 1: Comparator) (Address 64 Selector 1 Selector Comparator result register (Address Address ) 16 ...

Page 57

... Whether to connect the reference voltage input (V M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER der network or not depends on bit 5 of the A-D control register 1. The V pin is connected when bit 5 is “0” and is disconnected when bit REF 5 is “ ...

Page 58

... Fig. 71 A-D control register bit configuration 58 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER When the bit of comparator function select register is “0” and bit 3 of A-D control register 1 is “1”, A-D conversion ends after 59 f and the interrupt request bit of the A-D interrupt control register is set to “ ...

Page 59

... The A-D register can be read at any time. Be sure not to write to the A-D register corresponding to the pins se- lected for a comparator during operation. M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (5) Repeat sweep mode 1 Repeat sweep mode 1 is selected when bit 3 of A-D control register 0 is “1”, bit 4 is “1” and bit 2 of A-D control register 1 is “1”. ...

Page 60

... AV SS D-A Fig. 72 D-A converter block diagram 60 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER When A-D or D-A conversion is not performed, current from the V pin to the ladder network can be cut off by disconnecting ladder net- work from the V Before starting A-D or D-A conversion, wait for more after clearing bit 5 to “ ...

Page 61

... STP instruction. Refer to the section on the clock generating circuit for more details. The watchdog timer also becomes Hold state during Hold state and the clock input stopped. M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Clock source for peripheral devices Pf ...

Page 62

... Fig. 77 Reset circuit example (perform careful evaluation at system design before using) 62 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER INPUT/OUTPUT PINS Ports P0 to P11 all have the direction register and each bit can be programmed for input or output. A pin becomes an output pin when the corresponding bit of direction register is “ ...

Page 63

... Processor mode register ··· Processor mode register 1 16 Note : Bit 0 of chip select control register (address 62 Fig. 76 Microcomputer internal registers status after reset M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Watchdog timer Watchdog timer frequency select register 16 0 ...

Page 64

... P8 (Inside dotted-line included Data bus • Port Data bus Fig. 78 Block diagram for ports P0 to P11 in single-chip mode and E output (1) 64 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER , P10 to P10 ...

Page 65

... Port Data bus _ • E Fig. 79 Block diagram for ports P0 to P11 in single-chip mode and E output (2) M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Pull-up select Direction register Port latch “1” Direction register “0” Output Port latch ...

Page 66

... Figure 83) to “1” makes operation of the clock oscillation circuit stop, that is, the X stays at “H”, and the current consumption reduce. 66 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER X IN pin. IN ...

Page 67

... Fig. 82 Clock generating circuit block diagram M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 67 ...

Page 68

... When the signal output disable select bit = “1” and bit 5 = “1”, the E/RD pin outputs “L” independent of bit 6’s contents in execution of WIT or STP instruction. Fig. 83 Particular function select register 0 bit configulation 68 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 0 0 Particular function select register 0 This bit must be fixed to “ ...

Page 69

... Notes 1 : When the clock external input select bit is “1”, the clock oscillation circuit stops. An external clock can be input When the watchdog timer clock select bit is “1”, Wf M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER STP instruction When the STP instruction is executed, the oscillation circuit is stopped and the clock sources thermore, “ ...

Page 70

... Note : All functions of signal output disable select bit cannot be debugged using an debugger. 70 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER direction register and port latch in WIT/STP state like ports in single- chip mode. That is, when setting arbitrary data to the port latch and the contents of direction register to “ ...

Page 71

... Note : Clear bit 2 to “0” in low-speed running. Fig. 84 Processor mode register 0 bit configuration M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER • BYTE pin ) shown in When accessing the external memory, the level of the BYTE pin is 16 used to determine whether to use the data bus as 8-bit width or 16- bit width ...

Page 72

... The signal output stop disable bit (bit 4 of particular function select register 0) can stop E output in the single-chip mode and processor mode. Similarly, when accessing the internal memory in the memory expansion and microprocessor modes, RD and WR output can be fixed to “H”. Refer to Table 8 for details. 72 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 0 1 Memory expansion mode (Note 1) ...

Page 73

... When the BYTE pin’s level is “H” and the multiplex bus select bit (bit 5 of chip select area register; Figure 88) is “1”, port P10 functions as M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER follows during the bus cycle in which the external memory area cor- responding to the chip select CS • ...

Page 74

... P9 regardless of processor modes. For de- tails, refer to the following sections: output function of chip select sig- nal and address output function. 74 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Table 9. Relationship between CNV sor modes CNV SS • Single-chip • ...

Page 75

... The timing of Hold start and 16 termination is the same as that of addresses A tion on processor mode.) M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ___ ___ ...

Page 76

... When accessing the internal memory area Select function of bits 6 and 7 is valid when both the CS select control register) are “1”. Fig. 88 Chip select area register bit configuration 76 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1 0 Address Chip select area register ...

Page 77

... Fig. 89 Chip select areas M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 77 ...

Page 78

... MEMORY MODIFICATION FUNCTION The M37754M8C-XXXGP’s internal memory size and address area can be modified by set of bit 2 (memory allocation select bit) of the particular function select register 0. Figure 90 shows the memory al- location when modifying the internal memory area. Memory allocation select bit = “0” ...

Page 79

... Please send the following data for mask orders: <M37754M8C-XXXGP> (1) M37754M8C-XXXGP mask ROM order confirmation form (2) 100P6S mark specification form (3) ROM data (EPROM 3 sets) <M37754M8C-XXXHP> (1) M37754M8C-XXXHP mask ROM order confirmation form (2) 100P6Q mark specification form (3) ROM data (EPROM 3 sets) M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ...

Page 80

... P3, P8, P10, and P11 must less, the sum of I sum of I for ports P4, P5, P6, P7, and P9 must less. OH(peak) 3: When the clock source select bit is “1,” f(X running. 80 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Parameter , BYTE SS – –P2 ...

Page 81

... I IL RAM hold voltage V RAM Power supply current (target value Note: f MHz when the clock source select bit = “1.” IN M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER (Vcc = 5 V, Vss = – °C, f(X Test conditions – – – ...

Page 82

... The D-A register value of the unused D-A converter is “00 • The reference power supply input current of the ladder resistance of the A-D converter is excluded. 82 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER = – °C, the clock source select bit = 0, unless otherwise noted) a Test conditions ...

Page 83

... OUT t TAi input setup time su(UP-T ) OUT IN t TAi input hold time h(T -UP) OUT IN M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ( V± formulas of the limits are shown below. Also, the values at f Parameter Parameter f MHz MHz ...

Page 84

... Two-phase pulse input in event counter mode TAj input IN TAj input OUT Test conditions • • Input timing voltage : V = 1.0 V, VIH = 4 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Parameter tc (TA) t w(TAH) t w(TAL) t c(UP) w(UPH) t w(UPL su(UP-T ...

Page 85

... MHz) and when the count source is f(X IN A-D trigger input Symbol t AD input cycle time (minimum allowable trigger) c(AD) TRG t AD input low-level pulse width w(ADL) TRG M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Parameter Parameter f MHz IN f MHz IN f MHz IN ...

Page 86

... AD input TRG t CLKi TxDi RxDi INTi input Test conditions • Vcc = • Input timing voltage : • Output timing voltage : V = 0.8 V,V = 2.0 V M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP Parameter Parameter t c(TB) t w(TBL) t c(AD) w(ADL) t c(CK) w(CKH) t w(CKL d su w(INL) t w(INH) = 100 pF ...

Page 87

... Floating release delay time (at hold state) pzx(HLDA-DLZ/DHZ MHz when the clock source select bit = “1”. IN M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER = – °C, f MHz when the clock source select bit = “0” , unless Parameter = 5 V± ...

Page 88

... Test conditions • V± • RDY input, HOLD input : V • HLDA output 88 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER t t su(RDY 1-RDY) just before the RD and WR signals’ rise regardless of the bus mode and the number of waits ...

Page 89

... Intput timing voltage : • Output timing voltage : M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER = – °C, f MHz when the clock source select bit = “0” , unless Parameter ’s minimum limit is 50 ns. ...

Page 90

... When the clock source select bit = “1”, set t 3: Since the values depend on external clock input frequency f(X the next page. 90 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER = – °C, f MHz when the clock source select bit = “0” , unless ...

Page 91

... Port Pi data output delay time (i = 4—9, 11) d(WR–PiQ 12.5 MHz when the clock source selet bit = “1” IN Note: Since the values depend on external clock input frequency f(X M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER = 5 V± – °C, f ...

Page 92

... Floating release delay time t pzx(RD–DLZ) : f(X ) 12.5 MHz when the clock source select bit = “1” IN Note: When the clock source select bit is “1”, regard f(X 92 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER = 5 V± Parameter ...

Page 93

... While the address which corresponds to chip select signal CS Test conditions (except Port Pi, f(X • • Output timing voltage : • Data input : M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER w(H) w( ...

Page 94

... While the address which corresponds to chip select signal CS Test conditions (except Port Pi, f • • Output timing voltage : • Data input : M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER w(H) w( ...

Page 95

... CS Test conditions (except Port Pi, f(X IN • • Output timing voltage : • Data input : M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER w(H) w( ...

Page 96

... While the address which corresponds to chip select signal CS Test conditions (except Port Pi, f • • Output timing voltage : • Data input : M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER w(H) w( -RD) ...

Page 97

... While the address which corresponds to chip select signal CS Test conditions (except Port Pi, f • • Output timing voltage : • Data input : M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER w( ...

Page 98

... While the address which corresponds to chip select signal CS Test conditions (except Port Pi, f(X • • Output timing voltage : • Data input : M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER w(H) w( ...

Page 99

... When the clock source select bit = “1”, set t 3: Since the values depend on external clock input frequency f(X the next page. M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER = – °C, f(X )=40 MHz when the clock source select bit = “0” , unless ...

Page 100

... Port Pi data output delay time (i = 4—9, 11) d(WR–PiQ MHz when the clock source selet bit = “1” IN Note: Since the values depend on external clock frequency f(X 100 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER = 5 V± – °C, f Parameter ...

Page 101

... Floating release delay time pzx(RD–DLZ MHz when the clock source select bit = “1” IN Note: When the clock source select bit is “1”, regard f(X M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER = 5 V± Parameter low-level pulse width ) in tables as 2·f(X ). ...

Page 102

... Multiplex bus select bit = “1” • While the address which corresponds to chip select signal CS Test conditions (except Port Pi, f(X • • Output timing voltage : V OL • Data input : 102 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER w(H) w( ...

Page 103

... Multiplex bus select bit = “1” • While the address which corresponds to chip select signal CS Test conditions (except Port Pi, f(X • • Output timing voltage : V • Data input : M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER w(H) w( ...

Page 104

... While the address which corresponds to chip select signal CS Test conditions (except Port Pi, f(X • • Output timing voltage : • Data input : 104 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER w(H) w( ...

Page 105

... While the address which corresponds to chip select signal CS Test conditions (except Port Pi, f(X IN • • Output timing voltage : • Data input : M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER w(H) w( ...

Page 106

... While the address which corresponds to chip select signal CS Test conditions (except Port Pi, f • • Output timing voltage : • Data input : 106 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER -WR w(ALE) t ...

Page 107

... CS Test conditions (except Port Pi, f • • Output timing voltage : • Data input : M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER -RD w(ALE) ...

Page 108

... MHz when the clock source select bit = “1” f MHz when the clock source select bit = “1”. IN 108 M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER ) 40 MHz when the clock source select bit = “0” Parameter MITSUBISHI MICROCOMPUTERS MHz ...

Page 109

... Hi output 0— output (BYTE = “L”) 8— pzx(WR-DLZ/DHZ) Test conditions • • Output timing voltage : M37754M8C-XXXGP, M37754M8C-XXXHP M37754S4CGP, M37754S4CHP -WR) d( -WR w(WR) t d(ALE-WR) t h(WR-BHE) t h(WR-A) Address t h(WR-CS) ...

Page 110

... Mark specification Mark specification must be submitted using the correct form for the type of package being ordered fill out the appropriate 100P6S Mark Specification Form (for M37754M8C-XXXGP), 100P6Q Mark Specification Form (for M37754M8C-XXXHP) and attach to the Mask ROM Order Confirmation Form. 4. Comments ...

Page 111

... QFP) MARK SPECIFICATION FORM Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark 80 81 Mitsubishi lot number (6-digit or 7-digit) 100 1 B. Customer’s Parts Number + Mitsubishi catalog name ...

Page 112

... LQFP) MARK SPECIFICATION FORM Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark 75 76 Mitsubishi lot number (6-digit or 7-digit) 100 1 B. Customer’s Parts Number + Mitsubishi catalog name ...

Page 113

... These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. ...

Page 114

... Related page: page 63 (4) For the “timer A write flag (address 45 • New register name: timer A write register • New bit name: timer Ai write bit ( • Related pages: pages 8, 37, 40, 63 M37754M8C-XXXGP/HP DATA SHEET Revision Description ) are corrected: ...