X40010 Xicor, X40010 Datasheet
X40010
Related parts for X40010
X40010 Summary of contents
Page 1
... Instrumentation • Computer Systems —Computers —Network Servers DESCRIPTION The X40010/11/14/15 combines power-on reset con- trol, watchdog timer, supply voltage supervision, and secondary voltage supervision, in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying voltage to V circuit which holds RESET/RESET active for a period of time ...
Page 2
... V2MON comparator is supplied by V2MON (X40010/11 (X40014/15 RESET/ RESET Output. (X40011/15) This is an active LOW, open drain output which goes active when- ever V RESET CC thereafter. RESET Output. (X40010/14) This is an active HIGH CMOS output which goes active whenever V falls below V CC after Ground SS REV 1 ...
Page 3
... REV 1.3.4 7/12/02 Function impending power failure. For the X40010/11 the V2FAIL signal remains active until the V falling). It also remains active until V2MON returns and exceeds V monitors the power supply connected to the V2MON pin. ...
Page 4
... WDO signal going active. The state of two non- volatile control bits in the Status Register determines the watchdog timer period. The microprocessor can change these watchdog bits by writing to the X40010/ 11/14/15 control register (also refer to page 19). Figure 3. Watchdog Restart .6µs 1.3µ ...
Page 5
... See "Writing to the Control Registers" on page 7. The user must issue a stop, after sending this byte to the register, to initiate the nonvolatile cycle that stores WD1, WD0, PUP1, PUP0, BP1, and BP0. The X40010/ 11/14/15 will not acknowledge any data bytes written after the first byte is entered. ...
Page 6
... X40010/X40011/X40014/X40015 – Preliminary Figure 5. V Set/Reset Sequence ( TRIPX New V applied = X Old V applied + | Error | X Error < MDE WEL: Write Enable Latch (Volatile) The WEL bit controls the access to the memory and to the Register during a write operation. This bit is a vola- tile latch that powers up in the LOW (disabled) state. ...
Page 7
... X40010/X40011/X40014/X40015 – Preliminary PUP1, PUP0: Power Up Bits (Nonvolatile) The Power Up bits, PUP1 and PUP0, determine the time delay. The nominal power up times are t PURST shown in the following table. PUP1 PUP0 Power on Reset Delay ( 200ms (factory setting 400ms 1 1 800ms ...
Page 8
... X40010/X40011/X40014/X40015 – Preliminary Figure 6. Valid Data Changes on the SDA Bus SCL SDA At power-up, the Fault Detection Register is defaulted to all “0”. The system needs to initialize this register to all “1” before the actual monitoring take place. In the event of any one of the monitored sources failed. The corresponding bits in the register will change from a “ ...
Page 9
... X40010/X40011/X40014/X40015 – Preliminary Figure 7. Valid Start and Stop Conditions SCL SDA Serial Acknowledge Acknowledge is a software convention used to indicate successful data transfer. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data ...
Page 10
... X40010/X40011/X40014/X40015 – Preliminary Read Operation Prior to issuing the Slave Address Byte with the R/W bit set to one, the master must first perform a “dummy” write operation. The master issues the start condition and the Slave Address Byte, receives an acknowledge, then issues the Word Address Bytes. After acknowledging receipts of the Word Address Bytes, the master immedi- Figure 9 ...
Page 11
... X40010/X40011/X40014/X40015 – Preliminary Figure 10. Acknowledge Polling Sequence Byte Load Completed by Issuing STOP. Enter ACK Polling Issue START Issue Slave Address Byte (Read or Write) ACK Returned? YES High Voltage Cycle Complete. Continue Command Sequence? YES Continue Normal Read or Write Command Sequence PROCEED It should be noted that the ninth clock cycle of the read operation is not a “ ...
Page 12
... Signals from the Slave Figure 13. Random Address Read Sequence S t Signals from a the Master r t SDA Bus Signals from the Slave REV 1.3.4 7/12/02 Figure 11. X40010/11/14/15 Addressing Control Register Fault Detection Register Control Register Fault Detection Register S Slave t a Address ...
Page 13
... X40010/X40011/X40014/X40015 – Preliminary – One bit of the slave command byte is a R/W bit. The R/W bit of the Slave Address Byte defines the opera- tion to be performed. When the R/W bit is a one, then a read operation is selected. A zero selects a write operation. Word Address The word address is either supplied by the master or obtained from an internal counter. The internal counter is undefi ...
Page 14
... X40010/X40011/X40014/X40015 – Preliminary ABSOLUTE MAXIMUM RATINGS Temperature under bias ................... –65°C to +135°C Storage temperature ........................ –65°C to +150°C Voltage on any pin with respect to V ......................................–1.0V to +7V SS D.C. output current ............................................... 5mA Lead temperature (soldering, 10 seconds)........ 300°C RECOMMENDED OPERATING CONDITIONS Temperature Min. ...
Page 15
... X40010/X40011/X40014/X40015 – Preliminary D.C. OPERATING CHARACTERISTICS (Continued) (Over the recommended operating conditions unless otherwise specified) Symbol Parameter V Supply CC ( Trip Point Voltage Range TRIP1 CC ( V2FAIL RPD2 TRIP2 Second Supply Monitor I V2MON Current V2 (5) V V2MON Trip Point Voltage Range ...
Page 16
... X40010/X40011/X40014/X40015 – Preliminary EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR OUT 4.6K 2.06K RESET SDA WDO 30pF 30pF A.C. TEST CONDITIONS Input pulse levels V Input rise and fall times 10ns V Input and output timing levels Output load Standard output load REV 1.3.4 7/12/02 SYMBOL TABLE ...
Page 17
... X40010/X40011/X40014/X40015 – Preliminary A.C. CHARACTERISTICS Symbol f SCL Clock Frequency SCL t Pulse width Suppression Time at inputs IN t SCL LOW to SDA Data Out Valid AA t Time the bus free before start of new transmission BUF t Clock LOW Time LOW t Clock HIGH Time HIGH t Start Condition Setup Time ...
Page 18
... X40010/X40011/X40014/X40015 – Preliminary Write Cycle Timing SCL SDA th 8 Bit of Last Byte Nonvolatile Write Cycle Timing Symbol (1) t Write Cycle Time WC Note: ( the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. ...
Page 19
... X40010/X40011/X40014/X40015 – Preliminary RESET/RESET Timings V TRIP1 RESET V RVALID RESET LOW VOLTAGE AND WATCHDOG TIMING PARAMETERS Symbol ( RESET/RESET (Power down only) RPD1 TRIP1 ( V2FAIL RPDX TRIP2 Power On Reset delay: t PURST PUP1=0, PUP0=0 PUP1=0, PUP0=1 (factory setting) ...
Page 20
... X40010/X40011/X40014/X40015 – Preliminary Watchdog Time Out For 2-Wire Interface Start SCL SDA WDO Minimum Sequence to Reset WDT SCL SDA V Set/Reset Conditions TRIPX (V TRIPX t TSU WDO t VPS SCL 0 SDA A0h Start REV 1.3.4 7/12/02 Start Clockin ( RSP < t WDO Start V /V2MON ) ...
Page 21
... Program Voltage Off time before next cycle VPO V Programming Voltage Set Voltage Range TRAN1 TRIP1 V V Set Voltage Range – X40010/11 TRAN2 TRIP2 V V Set to Voltage Range – X40014/15 TRAN2A TRIP2 V V Set Voltage variation after programming (-40 to +85°C). tv TRIPX ...
Page 22
... X40010/X40011/X40014/X40015 – Preliminary PACKAGING INFORMATION Pin 1 Index 0.010 (0.25) 0.020 (0.50) 0° - 8° 0.016 (0.410) 0.037 (0.937) NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.3.4 7/12/02 8-Lead Plastic, SOIC, Package Code S8 Pin 1 0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7° 0.050 (1.27) X 45° 0.0075 (0.19) 0.010 (0.25) FOOTPRINT www.xicor.com ...
Page 23
... X40010/X40011/X40014/X40015 – Preliminary PACKAGING INFORMATION 0° – 8° Detail A (20X) See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.3.4 7/12/02 8-Lead Plastic, TSSOP, Package Code V8 .025 (.65) BSC .169 (4.3) .177 (4.5) .114 (2.9) .122 (3.1) .047 (1.20) .0075 (.19) .002 (.05) .006 (.15) .0118 (.30) .010 (.25) Gage Plane Seating Plane ...
Page 24
... X40010/X40011/X40014/X40015 – Preliminary ORDERING INFORMATION TRIP1 Range Range V TRIP2 2.9-5.5 4.6V±50mV 2.9V±50mV 2.6-5.5 4.4V±50mV 2.6V±50mV 1.7-3.6 2.9V±50mV 1.7V±50mV 1.3-3.6 2.9V±50mV 1.3V±50mV 1.3-3.6 2.6V±50mV 1.3V±50mV 1.0-3.6 2.9V±50mV 1.0V±50mV PART MARK INFORMATION REV 1.3.4 7/12/02 Operating Temperature Range Package Range o 8L SOIC - TSSOP - ...
Page 25
... X40010/X40011/X40014/X40015 – Preliminary LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. ...