X5325 Intersil Corporation, X5325 Datasheet - Page 8

• Manufacturer Part Number: X5325
• Description: (X5323 / X5325) CPU Supervisor with 32Kb SPI EEPROM
• Manufacturer: Intersil Corporation

The Write Enable Latch (WEL) bit indicates the sta-
tus of the write enable latch. When WEL = 1, the
latch is set HIGH and when WEL = 0 the latch is reset
LOW. The WEL bit is a volatile, read only bit. It can
be set by the WREN instruction and can be reset by
the WRDS instruction.
The block lock bits, BL0 and BL1, set the level of block
lock protection. These nonvolatile bits are programmed
using the WRSR instruction and allow the user to protect
one quarter, one half, all or none of the EEPROM array.
Any portion of the array that is block lock protected can
be read but not written. It will remain protected until the
BL bits are altered to disable block lock protection of that
portion of memory.
Figure 5. Read EEPROM Array Sequence
Register Bits
BL1
0
0
1
1
Status
SCK
SO
CS
SI
BL0
0
1
0
1
High Impedance
0
Array Addresses Protected
1
Instruction
None (factory default)
8
2
X5323/X5325
$0C00-$0FFF
$0800-$0FFF
$0000-$0FFF
3
4
5
6
7
15 14 13
8
X5323, X5325
9
16 Bit Address
10
The watchdog timer bits, WD0 and WD1, select the
watchdog time out period. These nonvolatile bits are
programmed with the WRSR instruction.
The FLAG bit shows the status of a volatile latch that
can be set and reset by the system using the SFLB
and RFLB instructions. The flag bit is automatically
reset upon power-up. This flag can be used by the
system to determine whether a reset occurs as a
result of a watchdog time out or power failure.
Notes: 1. The Watch Dog Timer is shipped disabled. (WD1 = 1,
20 21 22 23 24 25 26 27 28 29 30
3
Status Register Bits
WD1
2
0
0
1
1
2. The factory default for Memory Block Protection is
1
WD0 = 1)
‘None’. (BL1 = 0, BL0 = 0)
0
MSB
7
WD0
0
1
0
1
6
5
Data Out
4
disabled (factory default)
Watchdog Time Out
3
600 milliseconds
200 milliseconds
2
1.4 seconds
(Typical)
1
0
October 27, 2005
FN8131.1