M40Z100WMH1TR ST Microelectronics, M40Z100WMH1TR Datasheet - Page 2

• Manufacturer Part Number: M40Z100WMH1TR
• Description: NVRAM CONTROLLER for up to TWO LPSRAM
• Manufacturer: ST Microelectronics

M40Z111, M40Z111W
Table 2. Absolute Maximum Ratings
Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
Figure 2. SOIC Pin Connections
Warning: NC = Not Connected.
DESCRIPTION (cont’d)
When an invalid V
tioned chip enable (E
to write-protect the stored data in the SRAM.
2/12
Symbol
T
2. Soldering temperature not to exceed 260 C for 10 seconds (total thermal budget not to exceed 150 C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
T
SLD
V
V
V OUT
P
T
STG
I
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
CC
O
IO
V CC
V CC
A
D
THS
V SS
(2)
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Ambient Operating Temperature
Storage Temperature (V
Lead Solder Temperature for 10 seconds
Input or Output Voltages
Supply Voltage
Output Current
Power Dissipation
CC
M40Z111W
M40Z111
CON
condition occurs, the condi-
) output is forced inactive
AI02239B
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Parameter
V CC
E
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
E CON
NC
CC
(1)
Off)
SNAPHAT
SOIC
During a power failure, the SRAM is switched from
the V
to provide the energy required for data retention.
On a subsequent power-up, the SRAM remains
write protected until a valid power condition returns.
The 28 pin 330mil SOIC provides sockets with gold
plated contacts at both ends for direct connection
to a separate SNAPHAT housing containing the
battery. The unique design allows the SNAPHAT
battery package to be mounted on top of the SOIC
package after the completion of the surface mount
process. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to the
high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion. The SOIC and battery
packages are shipped separately in plastic anti-
static tubes or in Tape & Reel form. For the 28 lead
SOIC, the battery package (i.e. SNAPHAT) part
number is "M4Z28-BR00SH1" or "M4Z32-
BR00SH1" (See Table 7).
OPERATION
The M40Z111/111W, as shown in Figure 4, can
control up to two standard low-power SRAMs.
These SRAMs must be configured to have the chip
enable input disable all other input signals. Most
slow, low-power SRAMs are configured like this,
however many fast SRAMs are not. During normal
operating conditions, the conditioned chip enable
(E
pin with timing shown in Table 6. An internal switch
connects V
drop of less than 0.3V (I
CON
CC
) output pin follows the chip enable (E) input
pin to the lithium cell within the SNAPHAT
CC
–0.3 to V
to V
–0.3 to 7
–40 to 85
–55 to 125
OUT
0 to 70
Value
260
CC
20
1
. This switch has a voltage
OUT1
+0.3
).
Unit
mA
W
V
V
C
C
C