ISPLSI2128VL-100LB100 Lattice Semiconductor, ISPLSI2128VL-100LB100 Datasheet
ISPLSI2128VL-100LB100
Related parts for ISPLSI2128VL-100LB100
ISPLSI2128VL-100LB100 Summary of contents
Page 1
... Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
Page 2
Functional Block Diagram Figure 1. ispLSI 2128VL Functional Block Diagram (128-I/O and 64-I/O Versions) RESET Input Bus GOE 0 GOE 1 Output Routing Pool (ORP) Output Routing Pool (ORP) Megablock I I/O 1 ...
Page 3
Absolute Maximum Ratings Supply Voltage V ................................ -0.5 to +4.05V cc Input Voltage Applied ............................. -0.5 to +4.05V Off-State Output Voltage Applied .......... -0.5 to +4.05V Storage Temperature ................................ -65 to 150 C Case Temp. with Power Applied .............. -55 ...
Page 4
... Typical values are 2.5V and Maximum I varies widely with specific device configuration and operating frequency. Refer to Power Consumption CC section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum With no pull-up resistors. Specifications ispLSI 2128VL Figure 2 ...
Page 5
External Timing Parameters 3 TEST PARAMETER # COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay pd2 f max A 3 Clock Frequency with Internal Feedback f — 4 Clock Frequency ...
Page 6
Internal Timing Parameters 2 PARAMETER # Inputs t 20 Input Buffer Delay Dedicated Input Delay din GRP t 22 GRP Delay grp GLB Product Term Bypass Path Delay (Combinatorial) 4ptbpc Product ...
Page 7
Timing Model I/O Cell Ded. In #21 I/O Delay I/O Pin #20 (Input) #45 Reset #43, 44 Y0,1,2 GOE Derivations of su, h and co from the Product Term Clock Logic ...
Page 8
Power Consumption Power consumption in the ispLSI 2128VL device de- pends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax 200 180 160 ...
Page 9
Signal Descriptions Signal Name RESET Active Low (0) Reset pin resets all the registers in the device. GOE 0, GOE1 Global Output Enable input pins. Y0, Y1, Y2 Dedicated Clock Input – These clock inputs are connected to one of ...
Page 10
Signal Locations ...
Page 11
I/O Locations 208 176 160 Signal fpBGA TQFP PQFP I/O ...
Page 12
Signal Configuration ispLSI 2128VL 208-Ball fpBGA Signal Diagram I/O I/O I I/O I I/O I/O I ...
Page 13
Pin Configuration ispLSI 2128VL 176-Pin TQFP Pinout Diagram I/O 113 1 VCC 2 3 I/O 114 4 I/O 115 5 I/O 116 6 I/O 117 7 I/O 118 8 I/O 119 I/O 120 10 I/O 121 11 ...
Page 14
Pin Configuration ispLSI 2128VL 160-Pin PQFP Pinout Diagram 1 I/O 113 2 VCC 3 I/O 114 4 I/O 115 I/O 116 5 I/O 117 6 7 I/O 118 8 I/O 119 9 I/O 120 10 I/O 121 11 I/O 122 ...
Page 15
Signal Configuration ispLSI 2128VL 100-Ball caBGA Signal Diagram 10 9 I/O I I/O I I/O I I/O I GOE F VCC 0 TCK/ ...
Page 16
Pin Configuration ispLSI 2128VL 100-Pin TQFP Pinout Diagram RESET 11 VCC ...
Page 17
Part Number Description ispLSI 2128VL Device Family Device Number Speed f 150 = 150 MHz max f 135 = 135 MHz max f 100 = 100 MHz max ispLSI 2128VL Ordering Information FAMILY fmax (MHz) tpd (ns) 150 6.0 150 ...